參數(shù)資料
型號(hào)： EP7211
廠商： Cirrus Logic, Inc.
英文描述： HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
中文描述： 高性能超低功耗系統(tǒng)與LCD控制器芯片
文件頁(yè)數(shù)： 5/166頁(yè)
文件大?。?/td> 2623K
代理商： EP7211
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5
DS352PP3
JUL 2001
TABLE OF CONTENTS
1. CONVENTIONS........................................................................................................................11
1.1
Acronyms and Abbreviations...................................................................................................................11
1.2
Units of Measurement .............................................................................................................................12
1.3
General Conventions...............................................................................................................................12
1.4
Pin Description Conventions ...................................................................................................................12
2. PIN INFORMATION..................................................................................................................13
2.1
Pin Diagrams...........................................................................................................................................13
2.2
Pin Descriptions ......................................................................................................................................14
2.2.1
External Signal Functions...........................................................................................................15
2.3
256-Ball PBGA Ball Listing......................................................................................................................20
2.3.1
PBGA Ground Connections .......................................................................................................25
2.4
208-Pin LQFP Pin Listing........................................................................................................................26
2.5
JTAG Pin Ordering for 208-Pin LQFP Package ......................................................................................31
3. FUNCTIONAL DESCRIPTION.................................................................................................34
3.1
Main Functional Blocks ...........................................................................................................................35
3.2
CPU Core................................................................................................................................................37
3.3
Interrupt Controller ..................................................................................................................................37
3.3.1
Interrupt Latencies in Different States ........................................................................................39
3.3.1.1
Operating State ..........................................................................................................39
3.3.1.2
Idle State ....................................................................................................................40
3.3.1.3
Standby State.............................................................................................................40
3.4
Memory and I/O Expansion Interface......................................................................................................42
3.5
EP7211 Boot ROM..................................................................................................................................43
3.6
CL-PS6700 PC Card Controller Interface ...............................................................................................44
3.7
DRAM Controller with EDO Support .......................................................................................................47
3.8
Serial Interfaces ......................................................................................................................................51
3.8.1
Codec Sound Interface...............................................................................................................52
3.8.1.1
Codec Interrupt Timing...............................................................................................52
3.8.2
MCP Interface ............................................................................................................................53
3.8.2.1
MCP Operation ..........................................................................................................54
3.8.2.2
MCP Frame Format ...................................................................................................54
3.8.2.3
Audio and Telecom Sample Rates and Data Transfer ...............................................56
3.8.2.4
MCP FIFO Operation .................................................................................................58
3.8.2.5
MCP Codec Control Register Data Transfer..............................................................59
3.8.3
ADC Interface
—
Master Mode Only SSI1 (Synchronous Serial Interface) ...............................60
3.8.4
Master/Slave SSI2 (Synchronous Serial Interface 2).................................................................61
3.8.4.1
Read Back of Residual Data......................................................................................62
3.8.4.2
Support for Asymmetric Traffic...................................................................................63
3.8.4.3
Continuous Data Transfer ..........................................................................................63
3.8.4.4
Discontinuous Clock...................................................................................................63
3.8.4.5
Error Conditions .........................................................................................................64
3.8.4.6
Clock Polarity .............................................................................................................64
3.9
LCD Controller with Support for On-Chip Frame Buffer..........................................................................64
3.10 Internal UARTs (Two) and SIR Encoder..................................................................................................67
3.11 Timer Counters........................................................................................................................................67
3.11.1
Free Running Mode....................................................................................................................68
相關(guān)PDF資料
PDF描述
EP7211-CP-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CV-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7212 HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP7211(208LQFP) 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC
EP7211(256PBGA) 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC
EP7211-CB-D 制造商:Rochester Electronics LLC 功能描述:- Bulk
EP7211-CP-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CV-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
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