- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄362742 > EP7211 (Cirrus Logic, Inc.) HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER PDF資料下載
參數(shù)資料
| 型號(hào)： | EP7211 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| 中文描述： | 高性能超低功耗系統(tǒng)與LCD控制器芯片 |
| 文件頁(yè)數(shù)： | 41/166頁(yè) |
| 文件大?。?/td> | 2623K |
| 代理商： | EP7211 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)當(dāng)前第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
41
Functional Description
DS352PP3
JUL 2001
In the case where KBWEN is low and the INTMR2 bit 0 is low, it will only be possible to wakeup
the device by using the external
WAKEUP
pin or another enabled interrupt source. The keyboard
interrupt capability allows an OS to use either a polled or interrupt-driven keyboard routine, or a
combination of both.
NOTE:
The keyboard interrupt is NOT deglitched.
3.4
Memory and I/O Expansion Interface
Six separate linear memory or expansion segments are decoded by the EP7211, two of which can be
reserved for two PC Card cards, each interfacing to a separate single CL-PS6700 device. Each
segment is 256 Mbytes in size. Two additional segments (i.e., in addition to these six) are dedicated
to the on-chip SRAM and the on-chip ROM. The on-chip ROM space is fully decoded, and the
SRAM space is fully decoded up to the maximum size of the video frame buffer programmed in the
LCDCON register (128 kbytes). Beyond this address range the SRAM space is not fully decoded
(i.e., any accesses beyond 128 kbyte range get wrapped around to within 128 kbyte range). Any of
the six segments can be configured to interface to a conventional SRAM-like interface, and can be
individually programmed to be 8-, 16-, or 32-bits wide, to support page mode access, and to execute
from 1 to 4 wait states for non-sequential accesses and 0 to 3 for burst mode accesses. The zero wait
state sequential access feature is designed to support burst mode ROMs. For writeable memory
devices which use the
NMWE
pin, zero wait state sequential accesses are not permitted and one wait
state is the minimum which should be programmed in the sequential field of the appropriate
MEMCFG register. Bus cycles can also be extended using the
EXPRDY
input signal.
Page mode access is accomplished by setting SQAEN = 1, which enables accesses of the form one
random address followed by three sequential addresses, etc., while keeping
NCS
asserted. These
sequential bursts can be up to four words long before
NCS
is released to allow DMA and refreshes
to take place. This can significantly improve bus bandwidth to devices such as ROMs which support
page mode. When SQAEN = 0, all accesses to the ROM/SRAM/Flash are by random access without
NCS
being de-asserted between accesses. Again NCS is de-asserted after four consecutive accesses
to allow refreshes, etc.
Bits 5 and 6 of the SYSCON2 register independently enable the interfaces to the CL-PS6700 (PC
Card slot drivers). When either of these interfaces are enabled, the corresponding chip select (
NCS4
and/or
NCS5
) becomes dedicated to that CL-PS6700 interface. The state of SYSCON2 Bit 5
determines the function of chip select
NCS4
(i.e., CL-PS6700 interface or standard chip select
functionality); Bit 6 controls
NCS5
in a similar way. There is no interaction between these bits.
For applications that require a display buffer smaller than 38,400 bytes, the on-chip SRAM can be
used as the frame buffer and no external DRAM needs to be used.
The width of the boot device can be chosen by selecting values of
PE[1]
and
PE[0]
during power on
reset. These inputs are latched by the rising edge of
NPOR
to select the boot option.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP7211-CP-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7212 | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CB-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CV-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP7211(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211-CB-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP7211-CP-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。