參數(shù)資料
型號: EP7211
廠商: Cirrus Logic, Inc.
英文描述: HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
中文描述: 高性能超低功耗系統(tǒng)與LCD控制器芯片
文件頁數(shù): 36/166頁
文件大小: 2623K
代理商: EP7211
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
36
Functional Description
DS352PP3
JUL 2001
Figure 3-1. EP7211 Block Diagram
3.2
CPU Core
The ARM7TDMI core CPU is a 32-bit RISC processor, which is connected directly to the 8-kbyte
unified cache. This cache has 512 lines of 4 words, arranged as a 4-way set associative cache. The
cache is directly connected to the ARM7TDMI CPU, and therefore caches the virtual address from
the CPU. The MMU translates the virtual address into a physical address, it contains a 64-entry
translation look aside buffer (TLB) and is post cache; that is, it only translates external memory
references (cache misses) to save power.
The ARM7TDMI CPU, the MMU, the cache, and the write buffer together make up what is called
the ARM720T processor. See the
ARM720T Datasheet
for a complete description of the various
logic blocks that make up the processor, as well as all internal register information.
3.3
Interrupt Controller
The ARM720T has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The
interrupt controller in the EP7211 controls interrupts from 22 different sources. Seventeen interrupt
sources are mapped to the IRQ input and five sources to the FIQ input. FIQs have a higher priority
32.768-KHZ
OSCILLATOR
PLL
INTERRUPT
CONTROLLER
POWER
MANAGEMENT
SSI1 (ADC)
DRAM
CONTROLLER
LCD
CONTROLLER
ARM7TDMI
CPU CORE
8-KBYTE
CACHE
MMU
TIMER
COUNTERS (2)
CODEC
ARM720T
INTERNAL DATA BUS
PWM
3.6864 MHZ
32.768 KHZ
EINT[1
3], FIQ,
MEDCHG
BATOK, EXTPWR
PWRFL, BATCHG
PORTS A, B, D (8-BIT)
PORT E (3-BIT)
KEYBD DRIVERS (0
7)
BUZZER DRIVE
ADCCLK, ADCIN,
ADCOUT, SMPCLK,
ADCCS
SSICLK, SSITXFR,
SSITXDA, SSIRXDA,
SSIRSFR
UART2
IrDA
D0
D31
POR, RUN,
RESET, WAKEUP
EXPCLK, WORD,
CS[0
3], EXPRDY,
WRITE
MOE, MWE,
RAS[0
1], CAS[0
3]
A[0
27],
DRA[0
12]
LCD DRIVE
LED AND
PHOTODIODE
ASYNC
INTERFACE 1
ASYNC
INTERFACE 2
GPIO
INTERNAL ADDRESS BUS
13-MHZ INPUT
ON-CHIP
BOOT ROM
ON-CHIP SRAM
37.5 KBYTES
CL-PS6700
INTFC.
PB[0
1], CS[4
5]
EXPANSION
CONTROL
UART1
SSI2
APB BRIDGE
APB BUS
RTC
FLASHING LED DRIVE
ICE-JTAG
TEST AND
DEVELOPMENT
WRITE
BUFFER
MULTIMEDIA
CODEC PORT
STATE CONTROL
MEMORY CONTROL BLOCK
LCD DMA
DC-TO-DC
TM
相關(guān)PDF資料
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EP7211-CP-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
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