參數(shù)資料
型號(hào)： EP7211
廠商： Cirrus Logic, Inc.
英文描述： HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
中文描述： 高性能超低功耗系統(tǒng)與LCD控制器芯片
文件頁(yè)數(shù)： 150/166頁(yè)
文件大小： 2623K
代理商： EP7211
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
150
Test Modes
DS352PP3
JUL 2001
7.
TEST MODES
The EP7211 supports a number of hardware activated test modes, these are activated by the pin
combinations shown in the
Table 7-1. EP7211 Hardware Test Modes
. All latched signals will only
alter test modes while
NPOR
is low, their state is latched on the rising edge of
NPOR
. This allows
these signals to be used normally during various test modes.
Within each test mode, a selection of pins is used as multiplexed outputs or inputs to provide/monitor
the test signals unique to that mode.
7.1
Oscillator and PLL Bypass Mode
This mode is selected by
NTEST0
= 1
, NTEST1
= 0
.
In this mode all the internal oscillators and PLL are disabled and the appropriate crystal oscillator
pins become the direct external oscillator inputs bypassing the oscillator and PLL. MOSCIN must be
driven by a 36.864 MHz clock source and RTCIN by a 32.768 kHz source.
7.2
Oscillator and PLL Test Mode
This mode is selected by
NTEST0
= 0
, NTEST1
= 1, Latched
NURESET
= 0
This test mode will enable the main oscillator and it will output various buffered clock and test
signals derived from the main oscillator, PLL, and 32-kHz oscillator. All internal logic in the EP7211
will be static and isolated from the oscillators, with the exception of the 6-bit ripple counter used to
generate 576 kHz and the real time clock divide chain. Port A is used to drive the inputs of the PLL
directly, and the various clock and PLL outputs are monitored on the
COL
pins.
Table 7-2.
Table 7-1. EP7211 Hardware Test Modes
Test Mode
Latched
NMEDCHG
Latched
PE0
Latched
PE1
Latched
NURESET
NTEST0
NTEST1
Normal operation
(32-bit boot)
1
0
0
X
1
1
Normal operation
(8-bit boot)
1
1
0
X
1
1
Normal operation
(16-bit boot)
1
0
1
X
1
1
Alternative test ROM boot
0
X
X
X
1
1
Oscillator / PLL bypass
X
X
X
X
1
0
Oscillator / PLL test mode
X
X
X
0
0
1
ICE Mode
X
X
X
1
0
0
System test (all HiZ)
X
X
X
0
0
0
相關(guān)PDF資料
PDF描述
EP7211-CP-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CV-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7212 HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
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EP7211-CV-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
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