
1000 Mbits/s Receive Packet Transfer
4-7
The GMII interface starts receiving the preamble, SFD, and packet data
with the 125 MHz E1110_PHY_RX_CLK. The PCS_GMII_RXD[7:0] data
(for TBI mode) or E1110_RXD[9:0] data (for GMII mode) is synchronous
to this clock. The data and clock are then fed to an elasticity FIFO where
the received GMII data is synchronized to the local 125 MHz clock on
which the host interface and receive MAC engine operates. After the
E-1110 detects the preamble and SFD, it asserts MRX_SOP and
MRX_DVALID while driving the rst octet (MRX_DATA[7:0]) of the packet
onto the host receive interface bus. The data is then continuously output
on every rising edge of CLK125. Any time the MRX_ACK signal is
sampled deasserted, the E-1110 declares an underrun condition and
aborts the receive operation on the next clock. The E-1110 indicates the
aborted condition with the deassertion of MRX_DVALID. However, the
E-1110 still asserts MRX_EOP to indicate the end of packet condition of
the currently aborted packet.
The E-1110 asserts MRX_STATUS and drives the
MACRX_STATUS[41:0] lines, which contain the new RMON vector. The
RMON vector value is updated when MRX_STATUS is active; otherwise,
the value remains unchanged. The host can sample the status vector to
decide whether to drop or accept the packet. A number of conguration
conditions have an inuence over the status vector. If VLAN is enabled,
the E-1110 detects the VLAN frame ID and outputs the VLAN_PKT
signal. It also outputs the VLAN_ID, and VLAN_PRIORITY, and
VLAN_CFI signals from the 16-bit VLAN tag. In VLAN mode, VLAN
frames up to 1522 bytes are not declared as oversized. If the MAC
receives a packet larger than the allowed maximum size, the frame is
truncated and declared as a jabber frame. In such cases, the MRX_EOP
signal is asserted with the last byte transferred to the host, even though
technically it is not an end of frame.