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參數(shù)資料
| 型號： | E-1110 |
| 英文描述： | E-1110 10/100/1000 Mbits/s Ethernet MAC preliminary technical manual 4/01 |
| 中文描述： | 電子1110 10/100/1000 Mbits /秒以太網(wǎng)MAC初步的技術(shù)手冊4 / 01 |
| 文件頁數(shù)： | 49/108頁 |
| 文件大?。?/td> | 577K |
| 代理商： | E-1110 |
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Transmit Function Signals
3-7
received MTX_ACK signal. This assumes the host
requires the minimum IEEE 802.3 interframe gap (IFG) of
96 bits (12 bytes).
MTX_SOP is synchronous to CLK125 (125 MHz clock).
MTX_DVALID Transmit Data Valid
Input
MTX_DVALID, when asserted, indicates to the MAC that
valid frame data is present on the MTX_DATA[7:0] input
bus. If the MTX_DVALID input signal is deasserted while
the MTX_ACK output signal is asserted, a transmit data
underrun error condition is declared. The host interface
should change the data on the data bus only when the
MTX_DVALID and MTX_ACK are sampled active with the
rising edge of CLK125.
This signal is synchronous to CLK125 (125 MHz clock).
MTX_DATA[7:0]
Transmit Data
Input
The MTX_DATA[7:0] signals form the transmit data input
bus to the MAC. The data byte is clocked into the MAC
from the host transmit data buffer on each clock cycle
when both the MTX_DVALID and MTX_ACK signals are
asserted.
In Gigabit mode, MTX_DATA[7:0] is passed to
E1110_TXD[7:0] at the GMII, while maintaining the bit
ordering.
In the 10/100 Mbits/s mode, the data output sequence in
nibbles is MTX_DATA[0:3], then MTX_DATA[7:4]. Due to
the lower bandwidth requirement of the E-110 MAC, the
data transfer may not occur in a burst but rather in a
discontinuous manner.
The data is sampled synchronously with the positive
edge of the 125 MHz system clock.
MTX_EOP
Transmit End of Packet
Input
MTX_EOP, when asserted, indicates to the MAC that the
last byte or word of data for the current frame is present
on the MTX_DATA[7:0] input bus. The MTX_EOP input
signal should be asserted for the last transfer and should
be kept asserted until the host samples the MTX_ACK
signal on the positive edge of CLK125.
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