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參數(shù)資料
| 型號： | E-1110 |
| 英文描述： | E-1110 10/100/1000 Mbits/s Ethernet MAC preliminary technical manual 4/01 |
| 中文描述： | 電子1110 10/100/1000 Mbits /秒以太網(wǎng)MAC初步的技術(shù)手冊4 / 01 |
| 文件頁數(shù)： | 15/108頁 |
| 文件大?。?/td> | 577K |
| 代理商： | E-1110 |
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2-4
Functional Description
from the E-110 is written to a small, 4-deep,4x8 FIFO structure using
the 2.5/25 MHz MII receive clock. The data is then read out of the FIFO
using the 125 MHz host interface clock. The receive state machine
controls the FIFO and remaps the packet transfer protocol from the
E-110 to the E-1110. The state machine also implements a strip CRC
function that is not supported in the E-110 hard macro such that the
feature set for the E-110 and the Gigabit MAC are mapped one-to-one.
Besides providing the data and control interface logic, the Host Interface
module also generates a new RMON vector for the E-1110 from the
E-110 RMON vector and maps it exactly to the RMON vector generated
from the Gigabit MAC.
To interface to the transmit MAC engine of the E-110, the Host Interface
module uses a ping-pong buffer concept to ensure that the data is
properly synchronized to the 10/100 transmit MAC interface and the MAC
is never starved of any data during the packet transfer. The transmit
interface state machine handles the control protocol translation from the
E-110 transmit packet control protocol (E110_TPSF, E110_TPEF, and
E110_TPUD to MTX_SOP, MTX_DVALID, and MTX_ACK, respectively)
to the E-1110 transmit packet interface protocol.
The RMON vector from the E-110 is latched and synchronized to
125 MHz. A common multiplexed RMON vector is output to the host
interface over the RMON status vector pins of the E-1110.
The Host Interface module thus provides a common interface to the
system that hides the underlying MACs. The host then sees a single set
of clock and interface signals, even though the underlying MAC is either
the E-110 core operating at 10/100 Mbits/s or the Gigabit MAC operating
at 1000 Mbits/s.
2.1.2 Gigabit MAC Transmit Control Block
The Gigabit MAC transmit control block provides all of the logic required
to implement IEEE 802.3-compliant frame transmission. Data is accepted
from the host transmit interface through the Host Interface Module using
a synchronous handshake, processed through MAC data encapsulation
and frame assembly, and then delivered to the MAC GMII interface for
synchronous transfer to the PHY. The process of frame assembly
includes the attachment of preamble, start of frame delimiter, destination
address, source address, length, frame check sequence verication and
generation.
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