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參數(shù)資料
| 型號(hào)： | E-1110 |
| 英文描述： | E-1110 10/100/1000 Mbits/s Ethernet MAC preliminary technical manual 4/01 |
| 中文描述： | 電子1110 10/100/1000 Mbits /秒以太網(wǎng)MAC初步的技術(shù)手冊4 / 01 |
| 文件頁數(shù)： | 38/108頁 |
| 文件大小： | 577K |
| 代理商： | E-1110 |
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Clock Operation
2-25
2.3 Clock Operation
This section describes the operation of the clocks in the E-1110 core.
2.3.1 Clocks for 10/100 Mbits/s Mode
The core uses the following clocks for 10/100 Mbits/s operation:
Clocks from the PHY to the E-1110 MAC core:
–
E1110_PHY_RCLK
–
E1110_MII_TCLK.
Clocks from the E-1110 to the E-110 MAC core:
–
MII_TCLK
–
MII_RCLK
Clocks from the E-110 to the E-1110 MAC core:
–
E110_MTXC
–
E110_MRXC
Clock for the host packet bus interface: CLK125
The E-1110_PHY_RCLK, E1110_MII_TCLK, MII_TCLK, MII_RCLK,
E110_MTXC, and E110_MRXC clocks are basically the same transmit
and receive clocks from the PHY device to operate the core in the 10/100
mode. The E-1110 core, when congured in the 10/100 mode, congures
the PHY interface for the MII mode. The clocks input to the E-1110 PHY
interface are output over to the E-110 interface as MII signals after
passing through the multiplexer logic. The same MII clocks are input to
the E-1110 core as E110_MTXC and E110_MRXC instead of directly
using them internally. This is done to support a serial MII (SMII) interface,
if required. If an SMII interface is used, the entire Physical Interface
Multiplexer can be bypassed in the E-1110 core; however, in this case,
a separate multiplexer must be added outside the E-1110 core.
The transmit and receive clocks described above are input to the E-1110
core and used for ow control and part of the Host Interface module. The
clock frequencies are 2.5 MHz or 25 MHz. When the E-1110 core is
congured in Gigabit mode, the E-110 core drives the MII_TCLK and
MII_RCLK signals LOW. The clock frequency is 25% of the transmit data
rate. A PHY operating at 100 Mbits/s provides the E110_MTXC and
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