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參數(shù)資料
| 型號： | E-1110 |
| 英文描述： | E-1110 10/100/1000 Mbits/s Ethernet MAC preliminary technical manual 4/01 |
| 中文描述： | 電子1110 10/100/1000 Mbits /秒以太網(wǎng)MAC初步的技術(shù)手冊4 / 01 |
| 文件頁數(shù)： | 45/108頁 |
| 文件大小： | 577K |
| 代理商： | E-1110 |
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Receive Function Signals
3-3
3.1 Receive Function Signals
The host communicates with the E-1110 Gigabit MAC receive function
using the signals listed in this section. Signal direction is from the
perspective of the E-1110 core.
MRX_SOP
Receive Start of Packet
Output
The Receive Start of Packet (MRX_SOP) output signal,
when asserted, indicates that a new packet has been
received. This signal is asserted along with
MRX_DVALID and kept asserted until the host asserts
the MRX_ACK signal. The MAC asserts MRX_SOP
synchronously with the 125 MHz clock.
MRX_DVALID Receive Data Valid
Output
MRX_DVALID when asserted, indicates that valid data is
present on the MRX_DATA[7:0] output pins. When
MRX_ACK is sampled active with MRX_DVALID, the
MAC causes valid data to be placed on the
MRX_DATA[7:0] pins. If the MAC asserts the
MRX_DVALID output signal and the MRX_ACK input is
deasserted, a receive overow error condition is
declared. This signal is discontinuous in the 10/100 mode
of operation due to the MAC’s lower throughput. The
MAC synchronously asserts MRX_DVALID at 125 MHz.
MRX_DATA[7:0]
Receive Data
Output
The MRX_DATA[7:0] output signals form the receive data
bus. Each 8-bit data byte is clocked out of the MAC to the
host receive data buffer on each clock cycle when both
the MRX_DVALID and MRX_ACK signals are asserted.
Data is valid on the MRX_DATA[7:0] output bus for one
RX_CLK clock cycle. Bit ordering is maintained between
E1110_RXD[7:0] and MRX_DATA[7:0]. The MAC outputs
the data synchronously at 125 MHz.
MRX_EOP
Receive End of Packet
Output
MRX_EOP is asserted for one clock cycle to indicate the
end of packet. When MRX_EOP is asserted, the last
word is present on the MRX_DATA[7:0] pins. This signal
is asserted under all conditions, including aborted or
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