
E-110 Core Interface Signals
3-37
E110_HWD[10:0]
Host Random Number Generator
Output
The E110_HWD[10:0] signals contain the value of the
random number that the E-1110 loads into the MAC’s
Linear Feedback Shift Register (LFSR) to generate the
random number sequence used in collision backoff
timing. E110_HWD[10:0] must remain stable for two
MII_TCLK cycles after E110_LRNG is asserted.
E110_LRNG
Load Random Number Generator
Output
The E-1110 asserts the E110_LRNG signal to indicate
that the E110_HWD[10:0] signals are valid and the MAC
function should latch them. When the E-1110 deasserts
E110_LRNG, the E110_HWD[10:0] signals are not valid.
E110_LRNG must be synchronous to the MII_TCLK
clock and at least one MII_TCLK clock cycle wide, which
is 40 ns for 100 MHz operation and 400 ns for 10 MHz
operation The E110_HWD[10:0] signals must be stable
when the host pulses E110_LRNG.
E110_FC_FLS_CRS
Output
E-110 False Carrier Sense (Backpressure Control)
The E-1110 may use the E-110 core
E110_FC_FLS_CRS input pin to implement
backpressure. Backpressure makes the medium look
busy to other stations on the network who wish to send
data to the E-110 core. The E-1110 asserts the
E110_FC_FLS_CRS signal when a congestion threshold
for the port’s input buffer is reached. The E-1110 selects
the congestion threshold in such a way that it leaves
enough room in the buffer for the frame in progress.
When the E110_FC_FLS_CRS pin is asserted, the E-110
core waits until 44 bit times after the medium becomes
inactive (MII_CRS deasserted) and then starts sending
out a false carrier data pattern (alternate ones and
RSV4
Packet length bit 4.
RSV3
Packet length bit 3.
RSV2
Packet length bit 2.
RSV1
Packet length bit 1.
RSV0 (lsb)
Packet length bit 0.