參數(shù)資料
型號: E-1110
英文描述: E-1110 10/100/1000 Mbits/s Ethernet MAC preliminary technical manual 4/01
中文描述: 電子1110 10/100/1000 Mbits /秒以太網(wǎng)MAC初步的技術(shù)手冊4 / 01
文件頁數(shù): 101/108頁
文件大?。?/td> 577K
代理商: E-1110
5-2
Specications
5.1 Derivation of AC Timing and Loading
Delay predictor software is included with every core LSI Logic delivers
for incorporation into an ASIC. This software generates an input loading
report so you can plan for buffer strengths that drive core inputs.
A ramp time violation report is generated when you integrate the core
into the rest of logic and run simulations. The report indicates if a core
output is heavily loaded. Adjust buffering, wire length, and other
parameters to eliminate the violation.
There are no specic numbers in this chapter for AC timing and loading
because these parameters depend upon the technology used and the
design layout.
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