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參數(shù)資料
| 型號： | DSPE56007FJ66 |
| 英文描述： | DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC |
| 中文描述： | 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料 |
| 文件頁數(shù)： | 80/83頁 |
| 文件大?。?/td> | 382K |
| 代理商： | DSPE56007FJ66 |
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4-6
DSP56007/D
MOTOROLA
Design Considerations
Power-Up Considerations
POWER-UP CONSIDERATIONS
To power-up the device properly, ensure that the following conditions are met:
Stable power is applied to the device according to the specifications in
Table
2-3
(DC Electrical Characteristics).
The external clock oscillator is active and stable.
RESET is asserted according to the specifications in
Table 2-7
(Reset, Stop,
Mode Select, and Interrupt Timing).
The following input pins are driven to valid voltage levels: DR, PINIT,
MODA, MODB, and MODC.
Care should be taken to ensure that the maximum ratings for all input voltages obey
the restrictions on
Table 2-1
(Maximum Ratings), at all phases of the power-up
procedure. This may be achieved by powering the external clock, hardware reset, and
mode selection circuits from the same power supply that is connected to the power
supply pins of the chip.
At the beginning of the hardware reset procedure, the device might consume
significantly more current than the specified typical supply current. This is because of
contentions among the internal nodes being affected by the hardware reset signal
until they reach their final hardware reset state.
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