參數(shù)資料
型號(hào): DSPE56007FJ66
英文描述: DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述: 數(shù)字信號(hào)處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁(yè)數(shù): 47/83頁(yè)
文件大?。?/td> 382K
代理商: DSPE56007FJ66
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
MOTOROLA
DSP56007/D
2-23
SERIAL HOST INTERFACE (SHI) SPI PROTOCOL TIMING
(C
L
= 50 pF; V
IHS
= 0.7
×
V
CC
, V
ILS
= 0.3
×
V
CC
)
Table 2-12
Serial Host Interface (SHI) SPI Protocol Timing
No.
Characteristics
Mode
Filter
Mode
Expression
50 MHz
66 MHz
88 MHz
Unit
Min Max Min Max
Min
Max
Tolerable Spike Width
on Clock or Data In
bypassed
narrow
wide
0
20
100
0
20
100
0
20
100
ns
ns
ns
141 Minimum Serial Clock
Cycle = t
SPICC
(min)
For frequency below 33
MHz
1
For frequency above 33
MHz
1
CPHA = 0, CPHA = 1
2
CPHA = 1
master
slave
slave
bypassed
bypassed
narrow
wide
bypassed
narrow
wide
bypassed
narrow
wide
4
×
T
C
6
×
T
C
1000
2000
3
×
T
C
3
×
T
C
+ 25
3
×
T
C
+ 85
3
×
T
C
+ 79
3
×
T
C
+ 431
3
×
T
C
+ 1022
0.5
×
t
SPICC
–10
120
1000
2000
60
85
145
139
491
1082
91
1000
2000
45
70
130
124
476
1067
68.2
1000
2000
34.1
59.1
119.1
113.1
465.1
1056.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
142 Serial Clock High Period
CPHA = 0, CPHA = 1
2
CPHA = 1
master
slave
slave
bypassed
narrow
wide
bypassed
narrow
wide
T
C
+ 8
T
C
+ 31
T
C
+ 43
T
C
+ T
H
+ 40
T
C
+ T
H
+ 216
T
C
+ T
H
+ 511
0.5
×
t
SPICC
–10
50
28
51
63
70
246
541
35
23
46
58
63
239
534
24.1
19.4
42.4
54.4
57.0
233.0
528.0
ns
ns
ns
ns
ns
ns
ns
143 Serial Clock Low Period
CPHA = 0, CPHA = 1
2
CPHA = 1
master
slave
slave
bypassed
narrow
wide
bypassed
narrow
wide
T
C
+ 8
T
C
+ 31
T
C
+ 43
T
C
+ T
H
+ 40
T
C
+ T
H
+ 216
T
C
+ T
H
+ 511
10
2000
50
28
51
63
70
246
541
35
23
46
58
63
239
534
24.1
19.4
42.4
54.4
57.0
233.0
528.0
ns
ns
ns
ns
ns
ns
ns
144 Serial Clock Rise/ Fall
Time
master
slave
10
2000
10
2000
10
2000
ns
ns
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