參數(shù)資料
型號: DSPE56007FJ66
英文描述: DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述: 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁數(shù): 33/83頁
文件大?。?/td> 382K
代理商: DSPE56007FJ66
Specifications
External Memory Interface (EMI) DRAM Timing
MOTOROLA
DSP56007/D
2-9
EXTERNAL MEMORY INTERFACE (EMI) DRAM TIMING
(C
L
= 50 pF + 2 TTL Loads)
Table 2-8
External Memory Interface (EMI) DRAM Timing
No.
Characteristics
Symbol
Timing
Mode
Expression
50 MHz
66 MHz
88 MHz
Unit
Min Max Min Max Min Max
41 Page Mode Cycle Time
t
PC
slow
fast
slow
fast
slow
fast
slow
fast
4
×
T
C
3
×
T
C
7
×
T
C
– 16
5
×
T
C
– 16
3
×
T
C
– 10
2
×
T
C
– 10
3
×
T
C
+ T
L
– 7
2
×
T
C
+ T
L
7
0
80
60
124
84
50
30
63
43
61
46
90
60
35
20
46
30
45.5
34.1
63.5
40.8
24.1
12.7
32.8
21.4
ns
ns
ns
ns
ns
ns
ns
ns
42 RAS or RD Assertion to
Data Valid
43 CAS Assertion to Data
Valid
44 Column Address Valid
to Data Valid
t
RAC
,
t
GA
T
CAC
t
AA
45 CAS Assertion to Data
Active
46 RAS Assertion Pulse
Width
1
(Page Mode Access
Only)
47 RAS Assertion Pulse
Width
(Single Access Only)
48 RAS or CAS
Deassertation to RAS
Assertion
49 CAS Assertion Pulse
Width
50 Last CAS Assertion to
RAS Deassertation
(Page Mode Access
Only)
51 RAS or WR Assertion to
CAS Deassertation
52 RAS Assertion to CAS
Assertion
53 RAS Assertion to
Column Address Valid
T
CLZ
0
0
0
ns
t
RASP
slow
fast
3
×
T
C
–11
+ n
×
4
×
T
C
2
×
T
C
–11
+ n
×
3
×
T
C
7
×
T
C
– 11
5
×
T
C
– 11
209
149
156
110
114
79.9
ns
ns
t
RAS
slow
fast
129
89
95
65
68.5
45.8
ns
ns
t
RP
,
T
CRP
slow
fast
5
×
T
C
– 5
3
×
T
C
– 5
95
55
70
40
51.8
29.1
ns
ns
T
CAS
slow
fast
slow
fast
3
×
T
C
– 10
2
×
T
C
– 10
3
×
T
C
– 15
2
×
T
C
– 15
50
30
45
25
35
20
30
15
24.1
12.7
19.1
7.7
ns
ns
ns
ns
t
RSH
T
CSH
,
T
CWL
t
RCD
slow
fast
7
×
T
C
– 15
5
×
T
C
– 15
4
×
T
C
– 13
3
×
T
C
– 13
3
×
T
C
+ T
H
13
2
×
T
C
+ T
H
13
125
85
91
61
64.5
41.8
ns
ns
slow
fast
slow
67
47
57
47
32
40
32.5
21.1
26.8
ns
ns
ns
t
RAD
fast
37
25
15.4
ns
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