參數(shù)資料
型號: DSPE56007FJ66
英文描述: DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述: 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁數(shù): 42/83頁
文件大?。?/td> 382K
代理商: DSPE56007FJ66
2-18
DSP56007/D
MOTOROLA
Specifications
External Memory Interface (EMI) SRAM Timing
99 Address Valid to WR
Deassertation
100 Data Setup Time to WR
Deassertation
101 Data Hold Time from WR
Deassertation
102 WR Assertion to Data Valid
103 WR Deassertation to Data
high impedance
1
104 WR Assertion to Data
Active
T
CW
, t
AW
3
×
T
C
+ T
L
–14 +
Ws
×
T
C
T
C
+ T
L
– 5 +
Ws
×
T
C
T
H
– 6
56
39
25.8
ns
t
DS
(t
DW
)
25
18
12.0
ns
t
DH
4
2
0.1
ns
T
H
+ 4
T
H
+ 10
14
20
12
18
9.7
15.7
ns
ns
T
H
– 6
4
2
0.1
ns
Note:
1.
This value is periodically sampled and not 100% tested.
Figure 2-13
SRAM Read Cycle
Table 2-10
External Memory Interface (EMI) SRAM Timing
No.
Characteristics
Symbol
Expression
50 MHz
66 MHz
88 MHz
Unit
Min Max Min Max Min Max
MA0–MA14
MA15/
MCS3
MA16/
MCS2
/
MCAS
MA17/
MCS1
/
MRAS
MCS0
RD
WR
Data In
MD0–MD7
91
92
94
93
95
94
98
97
96
AA0267
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