參數(shù)資料
型號: DSPE56007FJ66
英文描述: DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述: 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁數(shù): 48/83頁
文件大?。?/td> 382K
代理商: DSPE56007FJ66
2-24
DSP56007/D
MOTOROLA
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
146 SS Assertion to First
SCK Edge CPHA = 0
CPHA = 1
slave
slave
bypassed
narrow
wide
bypassed
narrow
wide
T
C
+ T
H
+ 35
T
C
+ T
H
+ 35
T
C
+ T
H
+ 35
6
0
0
65
65
65
6
0
0
58
58
58
6
0
0
52.0
52.0
52.0
6
0
0
ns
ns
ns
ns
ns
ns
147 Last SCK Edge to SS Not
Asserted
CPHA = 0
CPHA = 1
3
slave
slave
bypassed
narrow
wide
bypassed
narrow
wide
T
C
+ 6
T
C
+ 70
T
C
+ 197
2
66
193
26
90
217
2
66
193
21
85
212
2
66
193
17.4
81.4
208.4
2
66
193
ns
ns
ns
ns
ns
ns
148 Data In Valid to SCK
Edge (Data In Set-up
Time)
master
slave
bypassed
narrow
wide
bypassed
narrow
wide
0
MAX {(37 –T
C
), 0}
MAX {(52 –T
C
), 0}
0
MAX {(38 –T
C
), 0}
MAX {(53 –T
C
), 0}
0
17
32
0
18
33
0
22
37
0
23
38
0
25.6
40.6
0
26.6
41.6
ns
ns
ns
ns
ns
ns
149 SCK Edge to Data In Not
Valid
(Data In Hold Time)
master
slave
bypassed
narrow
wide
bypassed
narrow
wide
2
×
T
C
+ 17
2
×
T
C
+ 18
2
×
T
C
+ 28
2
×
T
C
+ 17
2
×
T
C
+ 18
2
×
T
C
+ 28
4
57
58
68
57
58
68
47
48
58
47
48
58
39.7
40.7
50.7
39.7
40.7
50.7
ns
ns
ns
ns
ns
ns
150 SS Assertion to Data Out
Active
slave
4
4
4
ns
151 SS Deassertation to Data
high impedance
4
slave
24
24
24
24
ns
152 SCK Edge to Data Out
Valid (Data Out Delay
Time)
CPHA = 0, CPHA = 1
2
CPHA = 1
master
slave
slave
bypassed
narrow
wide
bypassed
narrow
wide
bypassed
narrow
wide
41
214
504
41
214
504
T
C
+ T
H
+ 40
T
C
+ T
H
+ 216
T
C
+ T
H
+ 511
41
214
504
41
214
504
70
246
541
41
214
504
41
214
504
63
239
534
41
214
504
41
214
504
57.0
233
528
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 2-12
Serial Host Interface (SHI) SPI Protocol Timing (Continued)
No.
Characteristics
Mode
Filter
Mode
Expression
50 MHz
66 MHz
88 MHz
Unit
Min Max Min Max
Min
Max
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