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參數(shù)資料
| 型號： | DSPE56007FJ66 |
| 英文描述： | DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC |
| 中文描述： | 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料 |
| 文件頁數(shù)： | 75/83頁 |
| 文件大?。?/td> | 382K |
| 代理商： | DSPE56007FJ66 |
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MOTOROLA
DSP56007/D
4-1
SECTION
4
DESIGN CONSIDERATIONS
THERMAL DESIGN CONSIDERATIONS
An estimation of the chip junction temperature, T
J
, in
°
C can be obtained from the
equation:
Equation 1:
Where:
T
A
= ambient temperature C
R
θ
JA
= package junction-to-ambient thermal resistance C/ W
P
D
= power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case
thermal resistance and a case-to-ambient thermal resistance:
Equation 2:
Where:
R
θ
JA
= package junction-to-ambient thermal resistance C/ W
R
θ
JC
= package junction-to-case thermal resistance C/ W
R
θ
CA
= package case-to-ambient thermal resistance C/ W
R
θ
JC
is device-related and cannot be influenced by the user. The user controls the
thermal environment to change the case-to-ambient thermal resistance, R
θ
CA
. For
example, the user can change the air flow around the device, add a heat sink, change
the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change
the thermal dissipation capability of the area surrounding the device on a PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow
is dissipated through the case to the heat sink and out to the ambient environment.
For ceramic packages, in situations where the heat flow is split between a path to the
case and an alternate path through the PCB, analysis of the device thermal
performance may need the additional modeling capability of a system level thermal
simulation tool.
T
J
T
A
P
D
R
θ
JA
×
(
)
+
=
R
θ
JA
R
θ
JC
R
θ
CA
+
=
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