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參數(shù)資料
| 型號： | DSPE56007FJ66 |
| 英文描述： | DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC |
| 中文描述： | 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料 |
| 文件頁數(shù)： | 31/83頁 |
| 文件大?。?/td> | 382K |
| 代理商： | DSPE56007FJ66 |
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Specifications
RESET, Stop, Mode Select, and Interrupt Timing
MOTOROLA
DSP56007/D
2-7
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
Table 2-7
Reset, Stop, Mode Select, and Interrupt Timing (C
L
= 50 pF + 2 TTL Loads)
No.
Characteristics
Min
Max
Unit
10
Minimum RESET assertion width:
PLL disabled
PLL enabled
1
Mode Select Setup Time
Mode Select Hold Time
Minimum Edge-triggered Interrupt Request Assertion
Width
16a Minimum Edge-triggered Interrupt Request
Deassertation Width
18 Delay from IRQA, IRQB, NMI Assertion to GPIO Valid
Caused by First Interrupt Instruction Execution
22
Delay from General Purpose Output Valid to Interrupt
Request Deassertation for Level Sensitive Fast
Interrupts—If Second Interrupt Instruction is:
2
Single Cycle
Two Cycles
25
Duration of IRQA Assertion for Recovery from Stop State
27
Duration for Level Sensitive IRQA Assertion to ensure
interrupt service (when exiting “STOP”)
Stable External Clock, OMR Bit 6 = 1
Stable External Clock, PCTL Bit 17 = 1
25
×
T
C
2500
×
ET
C
21
0
13
—
—
—
—
—
ns
ns
ns
ns
ns
14
15
16
13
—
ns
12
×
T
C
+ T
H
—
ns
T
L
– 31
(2
×
T
C
) + T
L
– 31
—
ns
ns
ns
12
6
×
T
C
+ T
L
12
—
—
ns
ns
Note:
1.
This timing requirement is sensitive to the quality of the external PLL capacitor connected to the PCAP
pin. For capacitor values
less than or equal to
2 nF, asserting RESET according to this timing requirement
will ensure proper processor initialization for capacitors with a deltaC/ C
less than
0.5%. (This is typical
for ceramic capacitors.) For capacitor values
greater than
2 nF, asserting RESET according to this timing
requirement will ensure proper processor initialization for capacitors with a deltaC/ C
less than
0.01%.
(This is typical for Teflon, polystyrene, and polypropylene capacitors.) However, capacitors with values
greater than
2 nF with a deltaC/ C
greater than
0.01% may require longer RESET assertion to ensure
proper initialization.
When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timing 22 applies to
prevent multiple interrupt service. To avoid these timing restrictions, the Negative Edge-triggered
mode is recommended when using fast interrupts. Long interrupts are recommended when using
Level-sensitive mode.
2.
Figure 2-2
Reset Timing
RESET
10
V
IHR
AA0251
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