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參數(shù)資料
| 型號： | DSPE56007FJ66 |
| 英文描述： | DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC |
| 中文描述： | 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料 |
| 文件頁數(shù)： | 55/83頁 |
| 文件大?。?/td> | 382K |
| 代理商： | DSPE56007FJ66 |
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Specifications
Serial Host Interface (SHI) I
2
C Protocol Timing
MOTOROLA
DSP56007/D
2-31
The Programmed Serial Clock Cycle, t
I
HDM0 and HRS bits of the HCKR (SHI Clock control Register).
2
CCP
, is specified by the value of the HDM5–
The expression for t
I
2
CCP
is:
where
HRS is the Prescaler Rate Select bit. When HRS is cleared, the fixed divide-by-
eight prescaler is operational. When HRS is set, the prescaler is bypassed.
HDM5–HDM0 are the Divider Modulus Select bits.
A divide ratio from 1 to 64 (HDM5–HDM0 = 0 to $3F) may be selected.
In I
2
C mode, you may select a value for the Programmed Serial Clock Cycle from
6
×
T
C
(HDM5–HDM0 = 2, HRS = 1)
1024
×
T
C
(HDM5–HDM0 = $3F, HRS = 0).
to
The DSP56007 provides an improved I
2
C bus protocol. In addition to supporting the
100 kHz I
2
C bus protocol, the SHI in I
2
C mode supports data transfers at up to 1000
kHz. The actual maximum frequency is limited by the bus capacitances (C
L
),the pull-
up resistors (R
P
), (which affect the rise and fall time of SDA and SCL, (see table
below)), and by the input filters.
Consideration for programming the SHI Clock Control Register (HCKR)—Clock
Divide Ratio: the master must generate a bus free time greater than T172 slave when
operating with a DSP56007 SHI I
2
C slave.
The table below describes a few examples
:
Table 2-14
Considerations for Programming the SHI Clock control Register (HCKR)
Conditions to be Considered
Resulting Limitations
Bus Load
Master
Oper-
ating
Freq.
Slave
Oper-
ating
Freq.
Master
Filter
Mode
Slave
Filter
Mode
T172
Slave
Min.
Perm-
issible
t
I
2
CCP
T172
Master
Maximum
I
2
C Serial
Frequency
C
L
= 50 pF,
R
P
= 2 k
88 MHz
88 MHz
Bypassed
Narrow
Wide
Bypassed
Narrow
Wide
36 ns
60 ns
95 ns
56
×
T
C
60
×
T
C
66
×
T
C
41 ns
66 ns
103 ns
1010 kHz
825 kHz
634 kHz
t
I
2
CCP
Tc
2
×
HDM[5:0]
1
+
(
)
×
7
1
HRS
–
(
)
×
1
+
(
)
×
[
]
=
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