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參數(shù)資料
| 型號： | DSPE56007FJ66 |
| 英文描述： | DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC |
| 中文描述： | 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料 |
| 文件頁數(shù)： | 28/83頁 |
| 文件大?。?/td> | 382K |
| 代理商： | DSPE56007FJ66 |
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2-4
DSP56007/D
MOTOROLA
Specifications
AC Electrical Characteristics
AC ELECTRICAL CHARACTERISTICS
The timing waveforms in the AC Electrical Characteristics are tested with a V
maximum of 0.5 V and a V
IH
minimum of 2.4 V for all pins, except EXTAL, RESET,
MODA, MODB, MODC, and SHI pins (MOSI/ HA0, SS/ HA2, MISO/ SDA, SCK/
SCL, HREQ). These pins are tested using the input levels set forth in the DC Electrical
Characteristics. AC timing specifications that are referenced to a device input signal
are measured in production with respect to the 50% point of the respective input
signal’s transition. DSP56007 output levels are measured with the production test
machine V
OL
and V
OH
reference levels set at 0.8 V and 2.0 V, respectively.
IL
All output delays are given for a 50 pF load unless otherwise specified.
For load capacitance greater than 50 pF, the drive capability of the output pins
typically decreases linearly:
1. At 1.5 ns per 10 pF of additional capacitance at all output pins except
MOSI/ HA0, MISO/ SDA, SCK/ SCL, HREQ
2. At 1.0 ns per 10 pF of additional capacitance at output pins MOSI/ HA0,
MISO/ SDA, SCK/ SCL, HREQ (in SPI mode only)
PLL supply current
—
0.7
1.1
—
1.0
1.5
—
1.3
2.2
mA
Input capacitance
3
C
IN
—
10
—
—
10
—
—
10
—
pF
Notes:
1.
2.
The SHI inputs are: MOSI/ HA0, SS/ HA2, MISO/ SDA, SCK/ SCL, and HREQ.
In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signals are
disabled during Stop state.
Periodically sampled and not 100% tested
Maximum values are derived using the methodology described in
application dependent and may vary widely from these numbers.
3.
4.
Section 4
. Actual maximums are
Table 2-3
DC Electrical Characteristics (Continued)
Characteristics
Symbol
50 MHz
66 MHz
88 MHz
Unit
Min Typ Max
Min Typ Max
Min Typ Max
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