參數(shù)資料
型號: DSPB56362AG120
廠商: Freescale Semiconductor
文件頁數(shù): 87/152頁
文件大?。?/td> 0K
描述: IC DSP 24BIT AUD 120MHZ 144-LQFP
標準包裝: 60
系列: DSP56K/Symphony
類型: 音頻處理器
接口: 主機接口,I²C,SAI,SPI
時鐘速率: 120MHz
非易失內(nèi)存: ROM(126 kB)
芯片上RAM: 42kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
Overview
DSP56362 Technical Data, Rev. 4
1-4
Freescale Semiconductor
– On-Chip Emulation (OnCE‘) module
– Joint Action Test Group (JTAG) test access port (TAP)
– Address trace mode reflects internal program RAM accesses at the external port
On-Chip Memories
— Modified Harvard architecture allows simultaneous access to program and data memories
— 30720 x 24-bit on-chip program ROM1 (disabled in 16-bit compatibility mode)
— 6144 x 24-bit on-chip X-data ROM1
— 6144 x 24-bit on-chip Y-data ROM1
— Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable
.
— 192 x 24-bit bootstrap ROM (disabled in sixteen-bit compatibility mode)
Off-Chip Memory Expansion
— Data memory expansion to 256K x 24-bit word memory for P, X, and Y memory using SRAM.
— Data memory expansion to 16M x 24-bit word memory for P, X, and Y memory using DRAM.
— External memory expansion port( twenty-four data pins for high speed external memory access
allowing for a large number of external accesses per sample)
— Chip select logic for glueless interface to SRAMs
— On-chip DRAM controller for glueless interface to DRAMs
Peripheral and Support Circuits
— Enhanced serial audio interface (ESAI) includes:
– Six serial data lines, 4 selectable as receive or transmit and 2 transmit only.
– Master or slave capability
–I2S, Sony, AC97, and other audio protocol implementations
— Serial host interface (SHI) features:
– SPI protocol with multi-master capability
–I2C protocol with single-master capability
– Ten-word receive FIFO
– Support for 8-, 16-, and 24-bit words.
— Byte-wide parallel host interface (HDI08) with DMA support
— DAX features one serial transmitter capable of supporting S/PDIF, IEC958, IEC1937, CP-340,
and AES/EBU digital audio formats; alternate configuration supports up to two GPIO lines
1. These ROMs may be factory programmed with data or programs provided by the application developer.
Instruction
Cache
Switch
Mode
Program RAM
Size
Instruction
Cache Size
X Data RAM Size Y Data RAM Size
Disabled
3072
× 24-bit
0
5632
× 24-bit
5632
× 24-bit
Enabled
Disabled
2048
× 24-bit
1024
× 24-bit
5632
× 24-bit
5632
× 24-bit
Disabled
Enabled
5120
× 24-bit
0
5632
× 24-bit
3584
× 24-bit
Enabled
4096
× 24-bit
1024
× 24-bit
5632
× 24-bit
3584
× 24-bit
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