參數(shù)資料
型號: DSPB56362AG120
廠商: Freescale Semiconductor
文件頁數(shù): 130/152頁
文件大?。?/td> 0K
描述: IC DSP 24BIT AUD 120MHZ 144-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: DSP56K/Symphony
類型: 音頻處理器
接口: 主機(jī)接口,I²C,SAI,SPI
時鐘速率: 120MHz
非易失內(nèi)存: ROM(126 kB)
芯片上RAM: 42kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
Serial Host Interface SPI Protocol Timing
DSP56362 Technical Data, Rev. 4
Freescale Semiconductor
3-53
144
Serial clock rise/fall time
Master
10
ns
Slave
2000
146
SS assertion to first SCK edge CPHA = 0
Slave
Bypassed
Narrow
Wide
3.5
×T
C+15
0
50
0
ns
CPHA = 1
Slave
Bypassed
Narrow
Wide
10
0
10
0
147
Last SCK edge to SS not asserted
slave
Bypassed
Narrow
Wide
12
102
189
12
102
189
ns
148
Data input valid to SCK edge (data input
set-up time)
Master/
Slave
Bypassed
Narrow
Wide
0
MAX{(20-TC), 0}
MAX{(40-TC), 0}
0
10
30
ns
149
SCK last sampling edge to data input not
valid
Master/
Slave
Bypassed
Narrow
Wide
2.5
×T
C+10
2.5
×T
C+30
2.5
×T
C+50
35
55
75
ns
150
SS assertion to data out active
Slave
2
ns
151
SS deassertion to data high impedance
Slave
9
9
ns
152
SCK edge to data out valid (data out delay
time)
Master/
Slave
Bypassed
Narrow
Wide
2
×T
C+33
2
×T
C+123
2
×T
C+210
53
143
230
ns
153
SCK edge to data out not valid
(data out hold time)
Master/
Slave
Bypassed
Narrow
Wide
TC+5
TC+55
TC+106
15
65
116
ns
154
SS assertion to data out valid (CPHA = 0)
Slave
TC+33
43
ns
157
First SCK sampling edge to HREQ output
deassertion
Slave
Bypassed
Narrow
Wide
2.5
×T
C+30
2.5
×T
C+120
2.5
×T
C+217
55
145
242
ns
158
Last SCK sampling edge to HREQ output
not deasserted (CPHA = 1)
Slave
Bypassed
Narrow
Wide
2.5
×T
C+30
2.5
×T
C+80
2.5
×T
C+136
55
105
161
ns
Table 3-21 Serial Host Interface SPI Protocol Timing (continued)
No.
Characteristics
Mode
Filter Mode
Expression
100MHz
Unit
Min
Max
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