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參數(shù)資料
| 型號(hào)： | DSPB56362AG120 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 82/152頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT AUD 120MHZ 144-LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | DSP56K/Symphony |
| 類型： | 音頻處理器 |
| 接口： | 主機(jī)接口，I²C，SAI，SPI |
| 時(shí)鐘速率： | 120MHz |
| 非易失內(nèi)存： | ROM（126 kB） |
| 芯片上RAM： | 42kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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Reset, Stop, Mode Select, and Interrupt Timing
DSP56362 Technical Data, Rev. 4
Freescale Semiconductor
3-9
27 Interrupt Requests Rate
HI08, ESAI, SHI, Timer
DMA
IRQ, NMI (edge trigger)
IRQ, NMI (level trigger)
12TC
8TC
12TC
—
120.0
80.0
120.0
—
100.0
66.7
100.0
ns
28 DMA Requests Rate
Data read from HI08, ESAI, SHI
Data write to HI08, ESAI, SHI
Timer
IRQ, NMI (edge trigger)
6TC
7TC
2TC
3TC
—
60.0
70.0
20.0
30.0
—
50.0
58.0
16.7
25.0
ns
29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
external memory (DMA source) access address out
valid
4.25
× T
C + 2.0
44.0
—
37.4
—
ns
1 V
CC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF
2 Use expression to compute maximum value.
3 Periodically sampled and not 100% tested.
4 For an external clock generator, RESET duration is measured during the time in which RESET is asserted, V
CC is valid, and the
EXTAL input is active and valid. For internal oscillator, RESET duration is measured during the time in which RESET is asserted
and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both
by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When
the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the device
circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize
this state to the shortest possible duration.
5 If PLL does not lose lock.
6 When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to
prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when
using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
7 These values depend on the number of wait states (WS) selected.
8 WS = number of wait states (measured in clock cycles, number of T
C.
9 This timing depends on several settings: For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and
oscillator disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before
executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to
set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee timings for that case.
For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization
delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored).
For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by
the PCTL Bit 17 and OMR Bit 6 settings.
For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The
PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel
with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay counter
completes count or PLL lock procedure completion. PLC value for PLL disable is 0.
The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency
(i.e., for 100 MHz it is 4096/100 MHz = 40.96
s). During the stabilization period, TC, TH, and TL will not be constant, and their
width may vary, so timing may vary as well.
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values1 (continued)
No
Characteristics
Expression2
100 MHz
120 MHz
Unit
Min
Max
Min
Max
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| DSPB56366AG120 | IC DSP 24BIT AUD 120MHZ 144-LQFP |
| DSPB56367AG150 | IC DSP 24BIT 150MHZ 144-LQFP |
| DSPB56371AF180 | IC DSP 24BIT 180MHZ 80-LQFP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSPB56362AG120 | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSPB56362PV100 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL AUDIO DSP - Bulk |
| DSPB56362PV120 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL AUDIO DSP - Bulk |
| DSPB56364AF100 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC DSP56364 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSPB56364FU100 | 制造商:Rochester Electronics LLC 功能描述:24 BIT AUDIO DSP - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
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