參數(shù)資料
型號： DSPB56362AG120
廠商： Freescale Semiconductor
文件頁數(shù)： 72/152頁
文件大?。?/td> 0K
描述： IC DSP 24BIT AUD 120MHZ 144-LQFP
標準包裝： 60
系列： DSP56K/Symphony
類型： 音頻處理器
接口： 主機接口，I²C，SAI，SPI
時鐘速率： 120MHz
非易失內(nèi)存： ROM（126 kB）
芯片上RAM： 42kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
JTAG/OnCE Interface
DSP56362 Technical Data, Rev. 4
2-20
Freescale Semiconductor
2.12
JTAG/OnCE Interface
Table 2-14 JTAG/OnCE Interface
Signal
Name
Type
State During Reset
Signal Description
TCK
Input
Test Clock—TCK is a test clock input signal used to synchronize the JTAG
test logic. It has an internal pull-up resistor.
This input is 5 V tolerant.
TDI
Input
Test Data Input—TDI is a test data serial input signal used for test
instructions and data. TDI is sampled on the rising edge of TCK and has an
internal pull-up resistor.
This input is 5 V tolerant.
TDO
Output
Tri-Stated
Test Data Output—TDO is a test data serial output signal used for test
instructions and data. TDO can be tri-stated and is actively driven in the
shift-IR and shift-DR controller states. TDO changes on the falling edge of
TCK.
TMS
Input
Test Mode Select—TMS is an input signal used to sequence the test
controller’s state machine. TMS is sampled on the rising edge of TCK and
has an internal pull-up resistor.
This input is 5 V tolerant.
TRST
Input
Test Reset—TRST is an active-low Schmitt-trigger input signal used to
asynchronously initialize the test controller. TRST has an internal pull-up
resistor.
The use of TRST is not recommended for new designs. It is recommended
to leave TRST disconnected.
This input is 5 V tolerant.
DE
Input/Output
Input
Debug Event—DE is an open-drain, bidirectional, active-low signal
providing, as an input, a means of entering the debug mode of operation
from an external command controller, and, as an output, a means of
acknowledging that the chip has entered the debug mode. This signal, when
asserted as an input, causes the DSP56300 core to finish the current
instruction being executed, save the instruction pipeline information, enter
the debug mode, and wait for commands to be entered from the debug serial
input line. This signal is asserted as an output for three clock cycles when
the chip enters the debug mode as a result of a debug request or as a result
of meeting a breakpoint condition. The DE has an internal pull-up resistor.
This is not a standard part of the JTAG TAP controller. The signal connects
directly to the OnCE module to initiate debug mode directly or to provide a
direct external indication that the chip has entered the debug mode. All other
interface with the OnCE module must occur through the JTAG port.
The use of DE is not recommended for new designs. It is recommended to
leave DE disconnected.
This input is not 5 V tolerant.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSPB56362AG120 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
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