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Application
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Date
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Programmer
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Sheet
C
56F853/854/855/857/858 Digital Signal Controller User Manual, Rev. 4
B-71
Freescale Semiconductor
Preliminary
ESSI Status Register (SSR) continued
Bits
7
Name
RDR
Description
Receive Data Ready Flag
This flag bit is set when Receive Data Register or the receive FIFO is loaded with a new
value. The RDR is cleared when the CPU reads the SRX register. When RXFIFO is enabled,
RDR is cleared when receive FIFO is empty.
Transmit Data Register Empty
This flag bit is set when there is no data waiting to be transferred to the TXSR register. A
transmit FIFO is enabled when there is at least one empty slot in STX or TXFIFO. When the
TXFIFO is not enabled, the STX is empty.
Receive Overrun Error
This flag bit is set when the Receive Shift Register (RXSR) is enabled, filled, ready to transfer
to the SRX or the RXFIFO registers, and when these registers are already full.
Transmitter Underrun Error
This flag bit is set when the TXSR is empty, or when there is no data to be transmitted, as
indicated by the TDE bit being set, and a transmit time slot occurs. When a Transmit Underrun
Error occurs, the previously sent data is retransmitted.
Transmit Frame Sync
When set, this flag bit indicates a frame sync occurred during transmission of the last word
written to the STX register.
Receive Frame Sync
When set, this flag bit indicates a frame sync occurred during receiving of the next word into
the SRX register.
Receive FIFO Full
When set, this bit indicates data can be read using the SRX register. The data level in the
RXFIFO must reach the your selected Receive FIFO Watermark (RFWM) threshold.
Transmit FIFO Empty
When set, the TFE bit indicates data can be written to the TXFIFO register. The TFE bit is
cleared by writing data to the STX register until the TXFIFO data content level reaches the
watermark level.
6
TDE
5
ROE
4
TUE
3
TFS
2
RFS
1
RFF
0
TFE
ESSI Status
Register (SSR)
Base + $4
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
IF1
IF0
TFF
TLS
RLS TF1ERR TF2ERR RDR TDE ROE TUE
TFS
RFS
RFF
TFE
Write
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ESSI
4 of 16
denotes Reserved Bits