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Memory Maps
Overview, Rev. 4
Freescale Semiconductor
3-15
Table 3-16. Enhanced Synchronous Serial Interface 0 Registers Address Map
(ESSI0_BASE = $1FFE20) see Chapter 12
Address Offset
Base + $0
Base + $1
Base + $2
Base + $3
Base + $4
Base + $5
Base + $6
Base + $7
Base + $8
Base + $9
Base + $A
Base + $B
Base + $C
Base + $D
Base + $E
Base + $F
Register Acronym
ESSI_0_STX0
ESSI_0_STX1
ESSI_0_STX2
ESSI_0_SRX
ESSI_0_SSR
ESSI_0_SCR2
ESSI_0_SCR3
ESSI_0_SCR4
ESSI_0_STXCR
ESSI_0_SRXCR
ESSI_0_STSR
ESSI_0_SFCSR
ESSI_0_TSMA
ESSI_0_TSMB
ESSI_0_RSMA
ESSI_0_RSMB
Register Name
Access Type
Write-Only
Write-Only
Write-Only
Read-Only
Read-Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Write-Only
Read-Only
Read/Write
Read/Write
Read/Write
Read/Write
Chapter Location
Section 12.8.1
Section 12.8.2
Section 12.8.3
Section 12.8.4
Section 12.8.7
Section 12.8.8
Section 12.8.9
Section 12.8.10
Transmit Register 0
Transmit Register 1
Transmit Regsiter 2
Receive Register
Status Register
Control Register 2
Control Register 3
Control Register 4
Transmit Control Register
Receive Control Register
Time Slot Register
FIFO Control / Status Register
Transmit Slot Mask Register
Transmit Slot Mask Register
Receive Slot Mask Register
Receive Slot Mask Register
Section 12.8.11
Section 12.8.12
Section 12.8.13
Section 12.8.14
Section 12.8.15
Table 3-17. Enhanced Synchronous Serial Interface 1 Registers Address Map
(ESSI1_BASE =$1FFE00) see Chapter 12
Address Offset
Base + $0
Base + $1
Base + $2
Base + $3
Base + $4
Base + $5
Base + $6
Base + $7
Base + $8
Base + $9
Base + $A
Base + $B
Base + $C
Base + $D
Base + $E
Base + $F
Register Acronym
ESSI_1_STX0
ESSI_1_STX1
ESSI_1_STX2
ESSI_1_SRX
ESSI_1_SSR
ESSI_1_SCR2
ESSI_1_SCR3
ESSI_1_SCR4
ESSI_1_STXCR
ESSI_1_SRXCR
ESSI_1_STSR
ESSI_1_SFCSR
ESSI_1_TSMA
ESSI_1_TSMB
ESSI_1_RSMA
ESSI_1_RSMB
Register Name
Access Type
Write-Only
Write-Only
Write-Only
Read-Only
Read-Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Write-Only
Read-Only
Read/Write
Read/Write
Read/Write
Read/Write
Chapter Location
Section 12.8.1
Section 12.8.2
Section 12.8.3
Section 12.8.4
Section 12.8.7
Section 12.8.8
Section 12.8.9
Section 12.8.10
Transmit Register 0
Transmit Register 1
Transmit Regsiter 2
Receive Register
Status Register
Control Register 2
Control Register 3
Control Register 4
Transmit Control Register
Receive Control Register
Time Slot Register
FIFO Control / Status Register
Transmit Slot Mask Register
Transmit Slot Mask Register
Receive Slot Mask Register
Receive Slot Mask Register
Section 12.8.11
Section 12.8.12
Section 12.8.13
Section 12.8.14
Section 12.8.15