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Module Memory Maps
Direct Memory Access (DMA), Rev. 4
Freescale Semiconductor
9-5
9.4 Module Memory Maps
The 5685x devices contain six independent DMA channels. Each DMA channel includes seven
user-programmable 16-bit registers. Base addresses of each register set are provided in
Table 9-4
through
Table 9-9
.
Table 9-4. DMA 0 Register Address Map (DMA0_BASE = $1FFEC0)
Address Offset
Base + $0
Base + $1
Base + $2
Base + $3
Base + $4
Base + $5
Base + $6
Register Acronym
DMA_3_TC
DMA_3_CQS
DMA_3_TC
DMA_3_DAL
DMA_3_DAH
DMA_3_SAL
DMA_3_SAH
Register Name
Transfer Control
Circular Queue Size
Transfer Count
Destination Address-Low
Destination Address-High
Source Address-Low
Source Address-High
Accesss Type
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Chapter Location
Section 9.6.1
Section 9.6.2
Section 9.6.3
Section 9.6.4
Section 9.6.5
Section 9.6.6
Section 9.6.7
Table 9-5. DMA 1 Register Address Map (DMA1_BASE = $1FFEC8)
Address Offset
Base + $0
Base + $1
Base + $2
Base + $3
Base + $4
Base + $5
Base + $6
Register Acronym
DMA_3_TC
DMA_3_CQS
DMA_3_TC
DMA_3_DAL
DMA_3_DAH
DMA_3_SAL
DMA_3_SAH
Register Name
Transfer Control
Circular Queue Size
Transfer Count
Destination Address-Low
Destination Address-High
Source Address-Low
Source Address-High
Accesss Type
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Chapter Location
Section 9.6.1
Section 9.6.2
Section 9.6.3
Section 9.6.4
Section 9.6.5
Section 9.6.6
Section 9.6.7
Table 9-6. DMA 2 Register Address Map (DMA2_BASE = $1FFED0)
Address Offset
Base + $0
Base + $1
Base + $2
Base + $3
Base + $4
Base + $5
Base + $6
Register Acronym
DMA_3_TC
DMA_3_CQS
DMA_3_TC
DMA_3_DAL
DMA_3_DAH
DMA_3_SAL
DMA_3_SAH
Register Name
Transfer Control
Circular Queue Size
Transfer Count
Destination Address-Low
Destination Address-High
Source Address-Low
Source Address-High
Access Type
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Chapter Location
Section 9.6.1
Section 9.6.2
Section 9.6.3
Section 9.6.4
Section 9.6.5
Section 9.6.6
Section 9.6.7