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Operating Modes
Serial Peripheral Interface (SPI), Rev. 4
Freescale Semiconductor
11-9
When the master SPI starts a transmission, the data in the slave Shift register begins shifting out
on the MISO pin. The slave can load its Shift register with new data for the next transmission by
writing to its Transmit Data register. The slave must write to its Transmit Data register at least
one bus cycle before the master begins the next transmission. Otherwise, the data already in the
slave Shift register shifts out on the MISO pin. Data written to the Slave Shift register during a
transmission remains in a buffer until the end of the transmission.
When the CPHA bit is set, the first edge of SCLK starts a transmission. When CPHA is cleared,
the falling edge of SS starts a transmission.
Note:
SCLK must be in the proper idle state before the slave is enabled to prevent SCLK
from appearing as a clock edge.
11.6.3 DMA Mode
When the TDMAEN or RDMAEM bits are set, the SPI operates in DMA mode. Normal SPTE
and/or SPRF interrupts are suppressed. Instead DMA requests are generated, signaling the DMA
controllers to read the SPDRR or SPDTR as needed. The DMA requests are suppressed in the
case of an OVRF or MODF interrupt, illustrated in
Figure 11-4
.
If the SPI is being used to send
and receive data, both TDMAEN and RDMAEN should be enabled/disabled at the same time. If
data is only being received or transmitted TDMAEN or RDMAEN may be left inactive as
appropriate, however in this case ERRIE must not be set to prevent the DMA request being
masked by a mode-fault error or overflow error. DMA mode must be used carefully. In the case
where CPHA=0, the SS signal to the slave is toggled by software between words. In DMA mode
there is no way of generating this pulse easily, so the DMA should not be used when CPHA=0.
Figure 11-4. SPI DMA Request Generation
Receive DMA Request
Transmit DMA Request
SPTE
SPRIE
MODF
OVRF
TDMAEN
MODF
OVRF
ERRIE
SPRF
RDMAEN