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Host Control Interrupt Vector
Overview, Rev. 4
Freescale Semiconductor
8-35
8.8 Wait and Stop Mode Operations
The system clocks and the 56800E are turned off during Wait and Stop modes. The ITCN will
signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the
IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop
mode. Also, the IRQA and IRQB signals automatically become low level sensitive in these
modes even if the Control Register bits are set to make them falling edge sensitive. This is
because there is no clock available to detect the falling edge.
8.9 Host Control Interrupt Vector
The Host Command IRQ, vector 49, acts differently than the other IRQs. The vector 49 value
driven onto the lower eight bits of VAB in response to this IRQ isn’t fixed as it is for the other
IRQs. The Host I/F module supplies these lower bits and the ITCN uses them when the interrupt
to the 56800E is in response to the Host Command IRQ. The ITCN also asserts the
HP_IRQ_ACK signal back to the Host Port module when the ITCN receives acknowledgement
from the CPU in response to the Host Command IRQ.
HI8
HI8
HI8
HI8
HI8
HI8
HI8
HI8
HI8
HI8
HI8
HI8
HI8
HI8
HI8
HI8
HI8
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
P:$DE
P:$E0
P:$E2
P:$E4
P:$E6
P:$E8
P:$EA
P:$EC
P:$EE
P:$F0
P:$F2
P:$F4
P:$F6
P:$F8
P:$FA
P:$FC
P:$FE
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Available for Host Command
Not on 855
Not on 855
Not on 855
Not on 855
Not on 855
Not on 855
Not on 855
Not on 855
Not on 855
Not on 855
Not on 855
Not on 855
Not on 855
Not on 855
Not on 855
Not on 855
Not on 855
N
Table 8-3. Interrupt Vector Table Contents (Continued)
Peripheral
Vector
Number
Priority
Level
Vector
Base
Address +
Interrupt Function
Chip
Exceptions