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Interrupts
Serial Peripheral Interface (SPI), Rev. 4
Freescale Semiconductor
11-29
The following items are reset only by a system reset:
The SPDTR and SPDRR Registers
All control bits in the SPSCR Register (MODFEN, ERRIE, SPR1, and SPR0)
The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, it is possible to clear SPE between
transmissions without having to set all control bits again when SPE is set back high for the next
transmission.
By not resetting the SPRF, OVRF, and MODF flags, it is possible to service the interrupts after
the SPI has been disabled. Disable SPI by writing 0 to the SPE bit. SPI can also be disabled by a
Mode Fault occurring in a SPI configured as a Master with MODF.
11.13 Interrupts
Four SPI status flags can be enabled to generate interrupt requests.
The following sources in the SPI Status and Control Register can generate interrupt requests:
The SPI Transmitter Interrupt Enable (SPTIE) bit enables the SPTE flag to generate
transmitter interrupt requests provided the SPI is enabled (SPE = 1). The clearing
mechanism for the SPTE flag is always just a write to the Data Transmit register.
The SPI Receiver Interrupt Enable (SPRIE) bit enables the SPRF bit to generate receiver
interrupt requests regardless of the state of the SPE bit. The clearing mechanism for the
SPRF flag is always just a read to the Data Receive register.
The Error Interrupt Enable (ERRIE) bit enables both the MODF and OVRF bits to
generate a receiver/error interrupt request.
The Mode Fault Enable (MODFEN) bit can prevent the MODF flag from being set so only
the OVRF bit is enabled by the ERRIE bit to generate receiver/error interrupt requests.
Table 11-6. SPI Interrupts
Flag
Request
SPTE (Transmitter Empty)
SPI Transmitter Interrupt Request (SPTIE = 1,SPE = 1)
SPRF (Receiver Full)
SPI Receiver Interrupt Request (SPRIE = 1)
OVRF (Overflow)
SPI Receiver/Error Interrupt Request (ERRIE = 1)
MODF (Mode Fault)
SPI Receiver/Error Interrupt Request (ERRIE = 1)