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DSC Side Registers
Host Interface Eight (HI8), Rev. 4
Freescale Semiconductor
16-15
16.8.3 HI8 Transmit Data Register (HTX)
The HI8 Transmit Data (HTX) register is used for DSC-to-Host data transfers. The HTX register
is viewed as a 16-bit
write-only
register by the DSC core. Writing to the HTX register clears the
HTDE bit in the HSR. The DSC can program the HTIE bit causing a Host Transmit Data inter-
rupt when the HTDE bit is set. The HTX register is transferred as 16-bit data to the receive byte
registers RXH/RXL when both the HTDE bit on the DSC Side and the RXDF status bits on the
Host Side are cleared. This transfer operation sets both RXDF and HTDE bits. Data should not be
written to the HTX register until the HTDE bit is set to prevent the previous data from being
overwritten.
Figure 16-7. HI8 Transmit Data Register (HTX)
See Programmer’s Sheet on Appendix page B - 139
16.8.4 HI8 Receive Data Register (HRX)
The HI8 Receive Data (HRX) register is used for Host-to-DSC data transfers. The HRX register
is viewed as a 16-bit
read-only
register by the DSC core. The HRX register is loaded with 16-bit
data from the Transmit Data registers TXH/TXL on the Host Side when both the Transmit Data
registers empty TXDE on the Host Side, and DSC Host Receive Data Full (HRDF) bits are
cleared. This transfer operation sets TXDE and HRDF bits. The HRX register contains valid data
when the HRDF bit is set. Reading HRX clears HRDF. The DSC may program the HRIE bit to
cause a Host Receive Data interrupt when HRDF is set.
Figure 16-8. HI8 Receive Data Register (HRX)
See Programmer’s Sheet on Appendix page B - 139
16.8.5 DSC Side Registers After Reset
Table 16-6
shows the results of the three reset types on the bits in each of the HI8 registers
accessible by the DSC core.
Base + $2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
HIGH BYTE (FROM HRX)
LOW BYTE (FROM LRX)
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Base + $2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
HIGH BYTE (FROM HTX)
LOW BYTE (FROM LTX)
Write
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0