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SPI Register Descriptions (SPI_BASE = $1FFFE8)
Serial Peripheral Interface (SPI), Rev. 4
Freescale Semiconductor
11-23
Note:
The maximum data transmission rate for the SPI is typically limited by the bandwidth
of the I/O drivers on the chip. Typical technology limits are normal at 40MHz and
10MHz for Wired OR. These apply to both Master and Slave modes. The BD field
needs to be set to keep the module within these ranges.
11.11.1.2 Data Shift Order (DSO)—Bit 12
This read/write bit determines whether the MSB or LSB bit is transmitted or received first. Both
Master and Slave SPI modules must transmit and receive the same length packets. Regardless
how this bit is set, when reading from the SPDRR or writing to the SPDTR, the LSB will always
be at bit location zero. If the data length is less than 16 bits, the data will be zero padded on the
upper bits.
0 = MSB transmitted first (MSB > LSB)
1 = LSB transmitted first (LSB > MSB)
11.11.1.3 Error Interrupt Enable (ERRIE)—Bit 11
This read/write bit enables the MODF and OVRF bits to generate interrupt requests. Reset clears
the ERRIE bit. The Error Interrupt Enable (ERRIE) bit enables both the MODF and OVRF bits to
generate a receiver/error interrupt request.
0 = MODF and OVRF cannot generate interrupt requests
1 = MODF and OVRF can generate interrupt requests
11.11.1.4 Mode Fault Enable (MODFEN)—Bit 10
This read/write bit, when set to one, allows the MODF flag to be set. If the MODF flag is set,
clearing the MODFEN does not clear the MODF flag.
If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI
configured as a master. For an enabled SPI configured as a slave, having MODFEN low only pre-
vents the MODF flag from being set. If configured as a Master and MODFEN = 1, a transmission
in progress will stop if SS goes low. It does not affect any other part of SPI operation.
Table 11-4. SPI Master Baud Rate Selection
SPR[2:0]
000
001
010
011
100
101
110
111
Baud Rate Divisor (BD)
2
4
8
16
32
64
128
256