參數(shù)資料
型號： DSP56367P
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： 數(shù)字信號處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號處理器
文件頁數(shù)： 10/100頁
文件大?。?/td> 1039K
代理商： DSP56367P
Interrupt and Mode Control
DSP56367 Technical Data, Rev. 2.1
2-6
Freescale Semiconductor
2.9
Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.
BR
Output
Output
(deasserted)
Bus Request
—BR is an active-low output, never tri-stated. BR is asserted when the
DSP requests bus mastership. BR is deasserted when the DSP no longer needs the
bus. BR may be asserted or deasserted independent of whether the DSP56367 is a
bus master or a bus slave. Bus “parking” allows BR to be deasserted even though the
DSP56367 is the bus master. (See the description of bus “parking” in the BB signal
description.) The bus request hold (BRH) bit in the BCR allows BR to be asserted under
software control even though the DSP does not need the bus. BR is typically sent to an
external bus arbitrator that controls the priority, parking, and tenure of each master on
the same external bus. BR is only affected by DSP requests for the external bus, never
for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset
to the bus slave state.
BG
Input
Ignored Input
Bus Grant
—BG is an active-low input. BG is asserted by an external bus arbitration
circuit when the DSP56367 becomes the next bus master. When BG is asserted, the
DSP56367 must wait until BB is deasserted before taking bus mastership. When BG is
deasserted, bus mastership is typically given up at the end of the current bus cycle.
This may occur in the middle of an instruction that requires more than one external bus
cycle for execution.
For proper BG operation, the asynchronous bus arbitration enable bit (ABE) in the
OMR register must be set.
BB
Input/
Output
Input
Bus Busy
—BB is a bidirectional active-low input/output. BB indicates that the bus is
active. Only after BB is deasserted can the pending bus master become the bus master
(and then assert the signal again). The bus master may keep BB asserted after ceasing
bus activity regardless of whether BR is asserted or deasserted. This is called “bus
parking” and allows the current bus master to reuse the bus without rearbitration until
another device requires the bus. The deassertion of BB is done by an “active pull-up”
method (i.e., BB is driven high and then released and held high by an external pull-up
resistor).
For proper BB operation, the asynchronous bus arbitration enable bit (ABE) in the OMR
register must be set.
BB requires an external pull-up resistor.
Table 2-7 External Bus Control Signals (continued)
Signal Name
Type
State During
Reset
Signal Description
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56367UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56371 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device
DSP56371AF180 制造商:Freescale Semiconductor 功能描述:
DSP56371D 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device
DSP56371UM 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:DSP56371UM
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