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參數(shù)資料
| 型號： | DSP56367P |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-Bit Audio Digital Signal Processor |
| 中文描述： | 24位音頻數(shù)字信號處理器 |
| 文件頁數(shù)： | 22/100頁 |
| 文件大?。?/td> | 1039K |
| 代理商： | DSP56367P |
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SPDIF Transmitter Digital Audio Interface
DSP56367 Technical Data, Rev. 2.1
2-18
Freescale Semiconductor
2.14
SPDIF Transmitter Digital Audio Interface
2.15
Timer
Table 2-13 Digital Audio Interface (DAX) Signals
Signal
Name
Type
State During
Reset
Signal Description
ACI
PD0
Input
Input, Output, or
Disconnected
GPIO
Disconnected
Audio Clock Input
—This is the DAX clock input. When programmed to use
an external clock, this input supplies the DAX clock. The external clock
frequency must be 256, 384, or 512 times the audio sampling frequency
(256
×
Fs, 384
×
Fs or 512
×
Fs, respectively).
Port D 0
—When the DAX is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 3.3V tolerant.
ADO
PD1
Output
Input, Output, or
Disconnected
GPIO
Disconnected
Digital Audio Data Output
—This signal is an audio and non-audio output in
the form of AES/EBU, CP340 and IEC958 data in a biphase mark format.
Port D 1
—When the DAX is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 3.3V tolerant.
Table 2-14 Timer Signal
Signal
Name
Type
State during
Reset
Signal Description
TIO0
Input or Output
Input
Timer 0 Schmitt-Trigger Input/Output
—When timer 0 functions as an
external event counter or in measurement mode, TIO0 is used as input. When
timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used
as output.
The default mode after reset is GPIO input. This can be changed to output or
configured as a timer input/output through the timer 0 control/status register
(TCSR0). If TIO0 is not being used, it is recommended to either define it as
GPIO output immediately at the beginning of operation or leave it defined as
GPIO input but connected to Vcc through a pull-up resistor in order to ensure
a stable logic level at this input.
This input is 3.3 V tolerant.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56367UM | 24-Bit Audio Digital Signal Processor |
| DSP56600 | Implementing Viterbi Decoders Using the VSL Instruction on DSP Families |
| DSP56852E | 16-bit Digital Signal Controllers |
| DSP56852VFE | 16-bit Digital Signal Controllers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56367UM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56371 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device |
| DSP56371AF180 | 制造商:Freescale Semiconductor 功能描述: |
| DSP56371D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device |
| DSP56371UM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:DSP56371UM |
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