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參數(shù)資料
| 型號： | DS2151Q |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | T1 Single-Chip Transceiver(T1單片收發(fā)器) |
| 中文描述： | DATACOM, FRAMER, PQCC44 |
| 封裝： | 0.652 INCH, PLASTIC, LCC-44 |
| 文件頁數(shù)： | 29/46頁 |
| 文件大?。?/td> | 307K |
| 代理商： | DS2151Q |
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DS2151Q
022698 29/46
clock is applied to the ACLKI pin, then it should be tied to
RVSS to prevent the device from falsely sensing a
clock. See Table 12–1. If the jitter attenuator is either
placed in the transmit path or is disabled, the RCLK out-
put can exhibit short high cycles of the clock. This is due
to the highly oversampled digital clock recovery cir-
cuitry. If the jitter attenuator is placed in the receive path
(as is the case in most applications), the jitter attenuator
restores the RCLK to being close to 50% duty cycle.
Please see the Receive AC Timing Characteristics in
Section 14 for more details.
SOURCE OF RCLK UPON RCL
Table 12–1
ACLKI PRESENT
RECEIVE SIDE JITTER
ATTENUATOR
TRANSMIT SIDE JITTER
ATTENUATOR
Yes
ACLKI via the jitter attenuator
ACLKI
No
centered crystal
TCLK via the jitter attenuator
12.2 Transmit Waveshaping and Line Driving
The DS2151Q uses a set of laser–trimmed delay lines
along with a precision Digital–to–Analog Converter
(DAC) to create the waveforms that are transmitted onto
the T1 line. The waveforms created by the DS2151Q
meet the latest ANSI, AT&T, and CCITT specifications.
See Figure 12–3. The user will select which waveform
is to be generated by properly programming the L0 to L2
bits in the Line Interface Control Register (LICR).
LBO SELECT IN LICR
Table 12–2
L2
L1
L0
LINE BUILD OUT
APPLICATION
0
0
0
0 to 133 feet/0 dB
DSX–1/CSU
0
0
1
133 to 266 feet
DSX–1
0
1
0
266 to 399 feet
DSX–1
0
1
1
399 to 533 feet
DSX–1
1
0
0
533 to 655 feet
DSX–1
1
0
1
–7.5 dB
CSU
1
1
0
–15 dB
CSU
1
1
1
–22.5 dB
CSU
Due to the nature of the design of the transmitter in the
DS2151Q, very little jitter (less then 0.005 UIpp broad-
Band from 10 Hz to 100 KHz) is added to the jitter pres-
ent on TCLK. Also, the waveforms that they create are
independent of the duty cycle of TCLK. The transmitter
in the DS2151Q couples to the T1 transmit twisted pair
via a 1:1.15 or 1:1.36 step up transformer as shown in
Figure 12–1. In order for the devices to create the
proper waveforms, the transformer used must meet the
specifications listed in Table 12–3.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2151Q/T&R | 制造商:Maxim Integrated Products 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC |
| DS2151Q/T&R | 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| DS2151QB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2151QB/T&R | 制造商:Maxim Integrated Products 功能描述:T1 SINGLE CHIP XCVR REV B T&R - Tape and Reel |
| DS2151QB/T&R+ | 制造商:Maxim Integrated Products 功能描述:FRAMER DS1/E1/ISDN-PRI/T1 5V 44PLCC - Tape and Reel |
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