- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385273 > DS2151Q (MAXIM INTEGRATED PRODUCTS INC) T1 Single-Chip Transceiver(T1單片收發(fā)器) PDF資料下載
參數(shù)資料
| 型號： | DS2151Q |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | T1 Single-Chip Transceiver(T1單片收發(fā)器) |
| 中文描述： | DATACOM, FRAMER, PQCC44 |
| 封裝： | 0.652 INCH, PLASTIC, LCC-44 |
| 文件頁數(shù)： | 28/46頁 |
| 文件大?。?/td> | 307K |
| 代理商： | DS2151Q |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
DS2151Q
022698 28/46
12.0 LINE INTERFACE FUNCTIONS
The line interface function in the DS2151Q contains
three sections; (1) the receiver which handles clock and
data recovery, (2) the transmitter which waveshapes
and drives the T1 line, and (3) the jitter attenuator. Each
of the these three sections is controlled by the Line Inter-
face Control Register (LICR) which is described below.
LICR: LINE INTERFACE CONTROL REGISTER
(Address=7C Hex)
(MSB)
(LSB)
L2
L1
L0
EGL
JAS
JABDS
DJA
TPD
SYMBOL
POSITION
NAME AND DESCRIPTION
L2
LICR.7
Line Build Out Select Bit 2
. Sets the transmitter build out; see the
Table 12–2
L1
LICR.6
Line Build Out Select Bit 1
. Sets the transmitter build out; see the Table 12–2
L0
LICR.5
Line Build Out Select Bit 0
. Sets the transmitter build out; see the Table 12–2
EGL
LICR.4
Receive Equalizer Gain Limit
.
0= –36 dB
1= –30 dB
JAS
LICR.3
Jitter Attenuator Select
.
0=place the jitter attenuator on the receive side
1=place the jitter attenuator on the transmit side
JABDS
LICR.2
Jitter Attenuator Buffer Depth Select
.
0=128 bits
1=32 bits (use for delay sensitive applications)
DJA
LICR.1
Disable Jitter Attenuator
.
0=jitter attenuator enabled
1=jitter attenuator disabled
TPD
LICR.0
Transmit Power Down
.
0=normal transmitter operation
1=powers down the transmitter and 3–states the TTIP and TRING pins
12.1 Receive Clock and Data Recovery
The DS2151Q contains a digital clock recovery system.
See the DS2151Q Block Diagram in Section 1 and Fig-
ure 12–1 for more details. The DS2151Q couples to the
receive T1 twisted pair via a 1:1 transformer. See Table
12–3 for transformer details. The DS2151Q automati-
cally adjusts to the T1 signal being received at the RTIP
and RRING pins and can handle T1 lines from 0 feet to
over 6000 feet in length. The crystal attached at the
XTAL1 and XTAL2 pins is multiplied by four via an inter-
nal PLL and fed to the clock recovery system. The clock
recovery system uses both edges of the clock from the
PLL circuit to form a 32 times oversampler which is used
to recover the clock and data. This oversampling tech-
nique offers outstanding jitter tolerance (see Figure
12–2). The EGL bit in the Line Interface Control Regis-
ter is used to limit the sensitivity of the receiver in the
DS2151Q. For most CPE applications, a receiver sen-
sitivity of –30 dB is wholly sufficient and hence the EGL
bit should be set to one. In some applications, more
sensitivity than –30 dB may be required and the
DS2151Q will allow the receiver to go as low as –36 dB if
the EGL bit is set to zero. However when the EGL bit is
set to zero, the DS2151Q will be more susceptible to
crosstalk and its jitter tolerance will suffer.
Normally, the clock that is output at the RCLK pin is the
recovered clock from the T1 AMI waveform presented
at the RTIP and RRING inputs. When no AMI signal is
present at RTIP and RRING, a Receive Carrier Loss
(RCL) condition will occur and the RCLK can be sourced
from either the ACLKI pin or from the crystal attached to
the XTAL1 and XTAL2 pins. The DS2151Q will sense
the ACLKI pin to determine if a clock is present. If no
LICR
相關PDF資料 |
PDF描述 |
|---|---|
| DS2154 | Enhanced E1 Single Chip Transceiver(改進型E1單片收發(fā)器) |
| DS2164Q | G.726 ADPCM Processor(G.726自適應音頻脈沖編碼處理器) |
| DS2175 | T1/CEPT Elastic Store(T1/CEPT 彈性存儲器) |
| DS2180A | T1 Transceiver(T1收發(fā)器) |
| DS2187 | Receive Line Interface(接收線接口) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS2151Q/T&R | 制造商:Maxim Integrated Products 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC |
| DS2151Q/T&R | 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| DS2151QB | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2151QB/T&R | 制造商:Maxim Integrated Products 功能描述:T1 SINGLE CHIP XCVR REV B T&R - Tape and Reel |
| DS2151QB/T&R+ | 制造商:Maxim Integrated Products 功能描述:FRAMER DS1/E1/ISDN-PRI/T1 5V 44PLCC - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。