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參數(shù)資料
| 型號(hào)： | DS2151Q |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | T1 Single-Chip Transceiver(T1單片收發(fā)器) |
| 中文描述： | DATACOM, FRAMER, PQCC44 |
| 封裝： | 0.652 INCH, PLASTIC, LCC-44 |
| 文件頁數(shù)： | 17/46頁 |
| 文件大?。?/td> | 307K |
| 代理商： | DS2151Q |
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DS2151Q
022698 17/46
LOOP UP/DOWN CODE DETECTION
Bits SR1.7 and SR1.6 will indicate when either the stan-
dard “l(fā)oop up” or “l(fā)oop down” codes are being received
by the DS2151Q. When a loop up code has been
received for 5 seconds, the CPE is expected to loop the
recovered data (without correcting BPVs) back to the
source. The loop down code indicates that the loopback
should be discontinued. See the AT&T publication TR
62411 for more details. The DS2151Q will detect the
loop up/down codes in both framed and unframed cir-
cumstances with bit error rates as high as 10**–2. The
loop code detector has a nominal integration period of
48 ms. Hence, after about 48 ms of receiving either
code, the proper status bit will be set to a one. After this
initial indication, it is recommended that the software
poll the DS2151Q every 100 ms to 500 ms until
5 seconds has elapsed to insure that the code is contin-
uously present. Once 5 seconds has passed, the
DS2151Q should be taken into or out of loopback via the
Remote Loopback (RLB) bit in CCR1.
SR2: STATUS REGISTER 2
(Address=21 Hex)
(MSB)
(LSB)
RMF
TMF
SEC
RFDL
TFDL
RMTCH
RAF
–
SYMBOL
POSITION
NAME AND DESCRIPTION
RMF
SR2.7
Receive Multiframe
. Set on receive multiframe boundaries.
TMF
SR2.6
Transmit Multiframe
. Set on transmit multiframe boundaries.
SEC
SR2.5
One Second Timer
. Set on increments of one second based on RCLK; will
be set in increments of 999 ms, 999 ms, and 1002 ms every 3 seconds.
RFDL
SR2.4
Receive FDL Buffer Full
. Set when the receive FDL buffer (RFDL) fills to
capacity (8 bits).
TFDL
SR2.3
Transmit FDL Buffer Empty
. Set when the transmit FDL buffer (TFDL)
empties.
RMTCH
SR2.2
. Set when the RFDL matches either
RFDLM1 or RFDLM2.
RAF
SR2.1
Receive FDL Abort
. Set when eight consecutive one’s are received in the
FDL.
–
SR2.0
Not Assigned
. Should be set to zero when written.
IMR1: INTERRUPT MASK REGISTER 1
(Address=7F Hex)
(MSB)
(LSB)
LUP
LDN
LOTC
SLIP
RBL
RYEL
RCL
RLOS
SYMBOL
POSITION
NAME AND DESCRIPTION
LUP
IMR1.7
Loop Up Code Detected
.
0=interrupt masked
1=interrupt enabled
LDN
IMR1.6
Loop Down Code Detected
.
0=interrupt masked
1=interrupt enabled
LOTC
IMR1.5
Loss of Transmit Clock
.
0=interrupt masked
1=interrupt enabled
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2151Q/T&R | 制造商:Maxim Integrated Products 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC |
| DS2151Q/T&R | 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| DS2151QB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2151QB/T&R | 制造商:Maxim Integrated Products 功能描述:T1 SINGLE CHIP XCVR REV B T&R - Tape and Reel |
| DS2151QB/T&R+ | 制造商:Maxim Integrated Products 功能描述:FRAMER DS1/E1/ISDN-PRI/T1 5V 44PLCC - Tape and Reel |
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