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參數(shù)資料
| 型號： | DS2151Q |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | T1 Single-Chip Transceiver(T1單片收發(fā)器) |
| 中文描述： | DATACOM, FRAMER, PQCC44 |
| 封裝： | 0.652 INCH, PLASTIC, LCC-44 |
| 文件頁數(shù)： | 25/46頁 |
| 文件大?。?/td> | 307K |
| 代理商： | DS2151Q |
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DS2151Q
022698 25/46
TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTERS
(Address=39 to 3B Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
SYMBOL
POSITION
NAME AND DESCRIPTION
CH24
TTR3.7
Transmit Transparency Registers
.
0=this DS0 channel is not transparent
1=this DS0 channel is transparent
CH1
TTR1.0
Each of the bit positions in the Transmit Transparency
Registers (TTR1/TTR2/TTR3) represent a DS0 chan-
nel in the outgoing frame. When these bits are set to a
one, the corresponding channel is transparent (or
clear). If a DS0 is programmed to be clear, no Robbed–
Bit signaling will be inserted nor will the channel have Bit
7 stuffing performed. However, in the D4 framing mode,
bit 2 will be overwritten by a zero when a Yellow Alarm is
transmitted. Also the user has the option to prevent the
TTR registers from determining which channels are to
have Bit 7 stuffing performed. If the TCR2.0 and
TCR1.3 bits are set to one, then all 24 T1 channels will
have Bit 7 stuffing performed on them regardless of how
the TTR registers are programmed. In this manner, the
TTR registers are only affecting which channels are to
have Robbed–Bit signaling inserted into them. Please
see Figure 13–9 for more details.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS
(Address=3C to 3E Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
SYMBOL
POSITION
NAME AND DESCRIPTION
CH24
TIR3.7
Transmit Idle Registers
.
0=do not insert the Idle Code into this DS0 channel
1=insert the Idle Code into this channel
CH1
TIR1.0
TIDR: TRANSMIT IDLE DEFINITION REGISTER
(Address=3F Hex)
(MSB)
(LSB)
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
TIDR0
SYMBOL
POSITION
NAME AND DESCRIPTION
TIDR7
TIDR.7
MSB of the Idle Code
TIDR0
TIDR.0
LSB of the Idle Code
Each of the bit positions in the Transmit Idle Registers
(TIR1/TIR2/TIR3) represent a DS0 channel in the out-
going frame. When these bits are set to a one, the corre-
sponding channel will transmit the Idle Code contained
in the Transmit Idle Definition Register (TIDR).
Robbed–Bit signaling and Bit 7 stuffing will occur over
the programmed Idle Code unless the DS0 channel is
made transparent by the Transmit Transparency Regis-
ters.
TTR1 (39)
TTR2 (3A)
TTR3 (3B)
TIR1 (3C)
TIR2 (3D)
TIR3 (3E)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS2151Q/T&R | 制造商:Maxim Integrated Products 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC |
| DS2151Q/T&R | 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| DS2151QB | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2151QB/T&R | 制造商:Maxim Integrated Products 功能描述:T1 SINGLE CHIP XCVR REV B T&R - Tape and Reel |
| DS2151QB/T&R+ | 制造商:Maxim Integrated Products 功能描述:FRAMER DS1/E1/ISDN-PRI/T1 5V 44PLCC - Tape and Reel |
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