參數(shù)資料
型號(hào)： DS2151Q
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 數(shù)字傳輸電路
英文描述： T1 Single-Chip Transceiver(T1單片收發(fā)器)
中文描述： DATACOM, FRAMER, PQCC44
封裝： 0.652 INCH, PLASTIC, LCC-44
文件頁(yè)數(shù)： 26/46頁(yè)
文件大?。?/td> 307K
代理商： DS2151Q
DS2151Q
022698 26/46
9.0 CLOCK BLOCKING REGISTERS
The
Receive
Channel
(RCBR1/RCBR2/RCBR3) and the Transmit Channel
Blocking Registers (TCBR1/TCBR2/TCBR3) control
the RCHBLK and TCHBLK pins respectively. The
RCHBLK and TCHCLK pins are user programmable
outputs that can be forced either high or low during indi-
Blocking
Registers
vidual channels. These outputs can be used to block
clocks to a UART or LAPD controller in Fractional T1 or
ISDN–PRI applications. When the appropriate bits are
set t o a one, the RCHBLK and TCHCLK pins will be held
high during the entire corresponding channel time. See
the timing in Section 13 for an example.
RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS
(Address=6C to 6E Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
SYMBOL
POSITION
NAME AND DESCRIPTION
CH24
RCBR3.7
Receive Channel Blocking Registers
.
0=force the RCHBLK pin to remain low during this channel time
1=force the RCHBLK pin high during this channel time
CH1
RCBR1.0
TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address=32 to 34 Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
SYMBOL
POSITION
NAME AND DESCRIPTION
CH24
TCBR3.7
Transmit Channel Blocking Registers
.
0=force the TCHBLK pin to remain low during this channel time
1=force the TCHBLK pin high during this channel time
CH1
TCBR1.0
10.0 ELASTIC STORES OPERATION
The DS2151Q has two onboard two–frame (386 bits)
elastic stores. These elastic stores have two main pur-
poses. First, they can be used to rate convert the T1
data stream to 2.048 Mbps (or a multiple of 2.048 Mbps)
which is the E1 rate. Secondly, they can be used to
absorb the differences in frequency and phase between
the T1 data stream and an asynchronous (i.e., not fre-
quency locked) backplane clock. Both elastic stores
contain full controlled slip capability which is necessary
for this second purpose. The receive side elastic store
can be enabled via CCR1.2 and the transmit side elastic
store is enabled via CCR1.7. The elastic stores can be
forced to a known depth via the Elastic Store Reset bit
(CCR3.6).
10.1 Receive Side
If the receive side elastic store is enabled (CCR1.2=1),
then the user must provide either a 1.544 MHz
(CCR1.3=0) or 2.048 MHz (CCR1.3=1) clock at the
SYSCLK pin. The user has the option of either providing
a frame sync at the RSYNC pin (RCR2.3=1) or having
the RSYNC pin provide a pulse on frame boundaries
(RCR2.3=0). If the user wishes to obtain pulses at the
frame boundary, then RCR2.4 must be set to zero and if
the user wishes to have pulses occur at the multiframe
boundary, then RCR2.4 must be set to one. If the user
selects to apply a 2.048 MHz clock to the SYSCLK pin,
then the data output at RSER will be forced to all ones
every fourth channel and the F–bit will be deleted.
Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots
0, 4, 8, 12, 16, 20, 24, and 28) will be forced to a one.
RCBR1 (6C)
RCBR2 (6D)
RCBR3 (6E)
TCBR1 (32)
TCBR2 (33)
TCBR3 (34)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2151Q/T&R 制造商:Maxim Integrated Products 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC
DS2151Q/T&R 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:*
DS2151QB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2151QB/T&R 制造商:Maxim Integrated Products 功能描述:T1 SINGLE CHIP XCVR REV B T&R - Tape and Reel
DS2151QB/T&R+ 制造商:Maxim Integrated Products 功能描述:FRAMER DS1/E1/ISDN-PRI/T1 5V 44PLCC - Tape and Reel
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