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參數(shù)資料
| 型號： | CY7C924DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 200-MBaud HOTLink Transceiver(200H波特?zé)峤硬迨瞻l(fā)器) |
| 中文描述： | 200 MBd的的HOTLink收發(fā)器（200小時(shí)波特?zé)峤硬迨瞻l(fā)器） |
| 文件頁數(shù)： | 9/58頁 |
| 文件大小： | 636K |
| 代理商： | CY7C924DX |
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CY7C924DX
PRELIMINARY
9
75
SPDSEL
Static control input
TTL levels
Normally wired HIGH
or LOW
Speed Select.
Used to select one of two operating data rate ranges for the device. When the
operating symbol rate is between 100 and 200 MBaud, SPDSEL must be
HIGH. When the operating symbol rate is between 50 and 100 MBaud,
SPDSEL must be LOW (see
Table 4
).
Range Select.
Selects the proper prescaler for the REFCLK input. See
Table 4
for the various
relationships between REFCLK, SPDSEL, RANGESEL, and BYTE8/10*.
When the Transmit FIFO is bypassed (FIFOBYP* is LOW), with RANGESEL
HIGH or SPDSEL LOW, TXFULL* toggles at half the REFCLK rate to provide
a character rate indication, and to show when data can be accepted.
External FIFO Select.
EXTFIFO modifies the active level of the RXEN* and TXEN* inputs and the
timing of the Transmitter and Receiver data buses. When not configured for
external FIFOs (EXTFIFO is LOW), TXEN* is assumed to be driven as a pipe-
line register and RXEN* is assumed to be driven by a controller for a pipeline
register. In this mode the active data transition for the transmit data bus is within
the same clock as the transmit interface is selected by TXEN*.
When configured for external FIFOs (EXTFIFO is HIGH), TXEN is assumed to
be driven by the empty flag of an attached CY7C42X5 FIFO, and RXEN is
assumed to be driven by the Almost Full flag of an attached CY7C42X5 FIFO.
In this mode the active data transition for the transmit data bus is in the clock
cycle following the clock edge where transmit interface is selected by TXEN*.
EXTFIFO also modifies the output state of the Receive and Transmit FIFO
flags. When configured for external FIFOs (EXTFIFO is HIGH), the Full and
Empty FIFO flags are active HIGH (the Half-full flag is always active LOW).
When not configured for external FIFOs (EXTFIFO is LOW), all of the FIFO
flags are active LOW.
FIFO Bypass Select. Active LOW.
When LOW, the Transmit and Receive FIFOs are bypassed. In this mode
TXCLK is not used. Instead all transmit data must be synchronous to REFCLK.
Transmit FIFO status flags are synchronized to REFCLK. All received data is
synchronous to the RXCLK output. Receive FIFO status flags are synchro-
nized to RXCLK (the recovered Receive PLL Character clock).
When HIGH, the Transmit and Receive FIFOs are enabled. In this mode all
Transmit FIFO writes are synchronized to TXCLK
,
and all Receive FIFO reads
are synchronous to the RXCLK input.
Encoder Bypass Select. Active LOW.
When LOW, both the Encoder and Decoder are bypassed. Data is transmitted
in NRZ format, without encoding, LSB first. Received data are presented as
parallel characters to the interface without decoding.
When HIGH, data is passed through both the 8B/10B Encoder in the Transmit
path and the Decoder in the Receive path.
Receive Discard Policy Select.
These inputs select between the four data handling and fill-character discard
modes in the receiver. See
Table 6
.
74
RANGESEL
Static control input
TTL levels
Normally wired HIGH
or LOW
49
EXTFIFO
Static control input
TTL levels
Normally wired HIGH
or LOW
28
FIFOBYP*
Static control input
TTL levels
Normally wired HIGH
or LOW
27
ENCBYP*
Static control input
TTL levels
Normally wired HIGH
or LOW
24, 25
RXMODE[1:0]
Static control input
TTL levels
Normally wired HIGH
or LOW
Pin Descriptions
(continued)
CY7C924DX HOTLink Transceiver
Pin #
Name
I/O Characteristics
Signal Description
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|---|---|
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| CY7C9528-BLC | 制造商:Cypress Semiconductor 功能描述:OC-12/3 (STM-4/1) FRAMER, 504 BGA - Bulk |
| CY7C9528-BLI | 制造商:Cypress Semiconductor 功能描述:OC-12/3 (STM-4/1) FRAMER, 504 BGA - Bulk |
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