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參數(shù)資料
| 型號： | CY7C924DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 200-MBaud HOTLink Transceiver(200H波特熱接插收發(fā)器) |
| 中文描述： | 200 MBd的的HOTLink收發(fā)器（200小時波特熱接插收發(fā)器） |
| 文件頁數(shù)： | 14/58頁 |
| 文件大?。?/td> | 636K |
| 代理商： | CY7C924DX |
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CY7C924DX
PRELIMINARY
14
bus, using the protocols defined in the ATM Forum UTOPIA
interface standards. It is enabled by setting EXTFIFO LOW.
In UTOPIA timing, the TXEMPTY* and TXFULL* outputs and
TXEN* input, are all active LOW signals. If the CY7C924DX is
addressed by AM*, it becomes
“
selected
”
when TXEN* is as-
serted LOW. Following selection, data is written into the Trans-
mit FIFO on every clock cycle where TXEN* remains LOW.
Cascade Timing Model
The Cascade timing model is a variation of the UTOPIA timing
model. Here the TXEMPTY* and TXFULL* outputs, and TXEN
input, are all active HIGH signals. Cascade timing makes use
of the same address and selection sequences as UTOPIA tim-
ing, but write data accesses use a delayed write. This delayed
write is necessary to allow direct coupling to external FIFOs,
or to state machines that initiate a write operation one clock
cycle before the data is available on the bus.
Cascade timing is enabled by setting EXTFIFO HIGH.
When used for FIFO depth expansion, Cascade timing allows
the size of the internal Transmit FIFO to be expanded to an
almost unlimited depth. It allows a CY7C42x5 series synchro-
nous FIFO to be attached to the transmit interface without any
extra logic, as shown in
Figure 3
.
Transmit FIFO
The Transmit FIFO is used to buffer data captured in the input
register for later processing and transmission. This FIFO is
sized to hold 256 14-bit characters. When the Transmit FIFO
is enabled, and a Transmit FIFO write is enabled (the device
is selected and TXEN* is sampled asserted), data and com-
mand are captured in the transmit input register and stored into
the Transmit FIFO. All Transmit FIFO write operations are
clocked by TXCLK.
The Transmit FIFO presents Full, Half-Full, and Empty FIFO
flags. These flags are provided synchronous to TXCLK. When
the Transmit FIFO is enabled, it allows operation with a Moore-
type external controlling state machine. When configured for
Cascade timing, the timing and active levels of these signals
are also designed to support direct expansion to Cypress
CY7C42x5 synchronous FIFOs.
Regardless of bus width (8- or 10-bit characters) the Transmit
FIFO can be clocked at any rate from DC to 50 MHz. This gives
the Transmit FIFO a maximum bandwidth of 50 million charac-
ters per second. Since the serial outputs can only move 20
million characters per second at their fastest operating rate,
there is ample time to service multiple CY7C924DX HOTLinks
with a single controller.
The read port of the Transmit FIFO is connected to a logic
block that performs data formatting and validation. All data
read operations from the Transmit FIFO are controlled by a
Transmit Control State Machine that operates synchronous to
REFCLK.
Transmit Formatter and Validation
The Transmit Formatter and validation logic performs three pri-
mary functions:
Parity checking
Data format control
Byte-packing
In addition to these logic functions, this block also controls the
timing for the transfer of data from the Transmit Input Register,
Transmit FIFO, or Elasticity Buffer.
Parity Checking
Parity checking is enabled in 8-bit encoded mode when the
internal FIFOs are disabled (FIFOBYP* is LOW) and PAREN
(TXSOC) is HIGH. ODD parity is supported, which requires at
least one bit of the data bus to always be a logic-1. The eight
data bits (TXDATA[7:0]), TXSC/D*, TXSVS, and TXOPIN
(TXDATA[8]) are covered by the parity checking hardware.
If a parity error is detected in a character, that character is not
transmitted, but is replaced with the C0.7 Exception character
(see Special Character codes in
Table 11
). This prevents bad
data from knowingly being transmitted and informs the receiv-
er that an error was detected in the source data stream.
Parity errors are reported to the transmit interface through the
TXPER output. This output pulses HIGH for one REFCLK pe-
riod, one or more cycles after the cycle where the parity error
was detected.
Transmit Data Formatting
The CY7C924DX supports a number of protocol enhance-
ments over a raw physical-layer device. These enhancements
are made possible in part through the use of the Transmit and
Receive FIFOs. These FIFOs allow the CY7C924DX to man-
age the data stream to a much greater extent than was possi-
ble before. In addition to the standard 8B/10B encoding used
to improve serial data transmission, the CY7C924DX also sup-
ports:
marking of packet or cell boundaries using TXSOC
an expanded command set
ability to address and route packets or frames to specific
receivers
All three of these capabilities are supported for both 8- and 10-
bit encoded character sizes, and are made possible through
use of the TXSOC bit. This bit is interpreted, along with
TXSC/D* and TXSVS, in those modes where both the Transmit
FIFO and the Encoder are enabled. All three bits determine
how the data associated with them is processed for transmis-
sion. These operations are listed in
Table 2
.
The entries in
Table 2
, where TXSOC is LOW generate the
same characters in the serial data stream as a standard
CY7B923 HOTLink Transmitter, which uses the ANSI standard
8B/10B character set. The data, command, and exception
character encodings are listed in the Data and Special Char-
Figure 3. External FIFO Depth Expansion of the
CY7C924DX Transmit Data Path
FF*
WEN*
D
TXCLK
FF*
WEN*
D
WCLK
EF*
REN*
Q
RCLK
TXEN
TXFULL
TXDATA
TXSC/D*
TXCLK
CY7C42x5 FIFO
CY7C924DX
EXTFIFO
“
1
”
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