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參數(shù)資料
| 型號(hào)： | CY7C924DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 200-MBaud HOTLink Transceiver(200H波特?zé)峤硬迨瞻l(fā)器) |
| 中文描述： | 200 MBd的的HOTLink收發(fā)器（200小時(shí)波特?zé)峤硬迨瞻l(fā)器） |
| 文件頁數(shù)： | 37/58頁 |
| 文件大?。?/td> | 636K |
| 代理商： | CY7C924DX |
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CY7C924DX
PRELIMINARY
37
data stream (without overfilling the Transmit FIFO). If the
Transmit FIFO ever goes empty, the Serializer is loaded with
an alternating disparity string of C5.0 (K28.5) sync characters
(when BYTE8/10* is HIGH) or the bit pattern 0110000100011
(when BYTE8/10* is LOW).
Depending on the system implementation this can be a signif-
icant issue. If the remote receiver is configured to decode
8B/10B coded characters, it will probably detect running dis-
parity errors because the bypassed Encoder is not able to
track the running disparity of the previously transmitted char-
acter. However, since these pre-encoded modes are generally
used with alternate forms of scrambling or encoding, this is not
generally an issue.
To maintain a data stream without adding these C5.0 SYNC
codes, it is necessary that the Transmit FIFO be loaded at or
faster than the rate that data is read from that FIFO.
CY7C924DX HOTLink Receive-Path
Operating Mode Descriptions
The HOTLink Receiver can be configured into several operat-
ing modes, each providing different capabilities and fitting dif-
ferent reception needs. These modes are selected using the
FIFOBYP*, ENBYP*, BYTE8/10*
inputs on the CY7C924DX
Transceiver. These modes can be reduced to five primary
classes:
Synchronous Decoded
Synchronous Undecoded
Asynchronous Decoded
Asynchronous Byte-Packed
Asynchronous Undecoded
In all these modes, serial data is received at one of the differ-
ential line receiver inputs and routed to the Deserializer and
Framer. The PLL in the clock and data recovery block is used
to extract a bit-rate clock from the transitions in the data
stream, and uses that clock to capture bits from the serial
stream. These bits are passed to the Deserializer where they
are formed into 10- or 12-bit characters.
To align the incoming bit stream to the proper character bound-
aries, the Framer must be enabled by asserting RFEN HIGH.
The Framer logic-block checks the incoming bit stream for the
unique pattern that defines the character boundaries. This log-
ic filter looks for the ANSI X3.230 symbol defined as a
“
Special
Character Comma
”
(K28.5 or C5.0). Once a K28.5 is found,
the Framer captures the offset of the data stream from the
present character boundaries, and resets the boundary to re-
flect this new offset, thus framing the data to the correct char-
acter boundaries.
Since noise induced errors can cause the incoming data to be
corrupted, and since many combinations of corrupt and legal
data can create an aliased K28.5, the framer may also be dis-
abled by deasserting RFEN LOW.
An option exists in the framer to require multiple K28.5 char-
acters, meeting specific criteria, before the character bound-
aries are reset. This multi-byte mode of the Framer is enabled
by keeping RFEN asserted HIGH for greater than approxi-
mately 2000 character clock cycles. For multi-byte framing, the
receiver must find a pair of K28.5 characters, both on identical
10-bit boundaries, within a 5-character span (50 bits).
Synchronous Decoded
In these modes, the Receive FIFO is bypassed, while the
10B/8B Decoder is enabled. Framed characters output from
the Deserializer are decoded, and passed direct to the Re-
ceive Output Register. The Deserializer operates synchronous
to the recovered bit-clock, which is divided by 10 generate the
output RXCLK clock. In this mode the RXRST* input is not
interpreted and may be biased either HIGH or LOW.
These modes are usually used for products that must meet
specific protocol requirements. New decoded characters are
provided at the RXDATA outputs once every rising edge of
RXCLK. If RXEMPTY is asserted HIGH along with the data,
the characters in the output register is a C5.0 (K28.5) sync
character, and the discard policy is set to non-0. Because the
decoder is now enabled, all received characters are checked
for compliance to the 8B/10B decoding rules.
Output Register Mapping
The RXDATA[11:0] output bus is mapped into a character con-
sisting of eight bits of data, and two bits that carry Violation and
Parity information. An accompanying RXSC/D* bit identifies
the character as either control or data.
The bits accompanying each character are interpreted differ-
ently depending on the configuration selected. When parity
generation is enabled, the parity bit contains the ODD parity of
the RXDATA bus.
When parity generation is disabled, these bits have combina-
tions that identify the meaning of the remaining bits of the char-
acter. If RXRVS is HIGH and RXSC/D* is LOW, the decoder
outputs a C0.7, C1.7, C2.7 or C4.7 in response to reception of
either an SVS (C0.7) character or other invalid character.
Parity
Synchronous Decoded modes allows ODD parity generation
on all decoded characters. If characters are detected with par-
ity errors in the transmitter, they will have been replaced with
the SVS (C0.7) character. If a C0.7 character is received it may
be an indication of a parity error at the transmitter.
Synchronous Undecoded
In this mode, both the Receive FIFO and the 10B/8B Decoder
are bypassed, and data passes directly from the Deserializer
to the output register. The Deserializer operates synchronous
to the recovered bit-clock, which is divided by 10 to generate
the output RXCLK clock. In this mode the RXRST* input is not
interpreted and may be biased either HIGH or LOW.
This mode is usually used for products containing external de-
coders or descramblers that must meet specific protocol re-
quirements. New data is provided at the RXDATA outputs once
every rising edge of RXCLK. Received characters are not
checked for any specific coding requirements and no decoding
errors are reported.
Asynchronous Decoded
Asynchronous Decoded modes are the most powerful operat-
ing modes of the CY7C924DX HOTLink Receiver. Both the
Receive FIFO and the Decoder are enabled. This allows re-
ception of normal data streams, while offering the added ben-
efits of embedded cell markers, an expanded command set,
serial address support, and in-band bypass-signaling (for flow
control or other purposes). All characters added to the data
stream to support these additional capabilities may be auto-
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C9335-270AC | 制造商:Cypress Semiconductor 功能描述:Descrambler/Framer Controller 100-Pin TQFP |
| CY7C9335A-270AXC | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SMPTE Decoder COM RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CY7C9335A-270AXCT | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SMPTE Decoder COM RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CY7C9528-BLC | 制造商:Cypress Semiconductor 功能描述:OC-12/3 (STM-4/1) FRAMER, 504 BGA - Bulk |
| CY7C9528-BLI | 制造商:Cypress Semiconductor 功能描述:OC-12/3 (STM-4/1) FRAMER, 504 BGA - Bulk |
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