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參數(shù)資料
| 型號： | CY7C924DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 200-MBaud HOTLink Transceiver(200H波特熱接插收發(fā)器) |
| 中文描述： | 200 MBd的的HOTLink收發(fā)器（200小時波特熱接插收發(fā)器） |
| 文件頁數(shù)： | 8/58頁 |
| 文件大?。?/td> | 636K |
| 代理商： | CY7C924DX |
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CY7C924DX
PRELIMINARY
8
19
RXHALF*
TTL output, changes
following RXCLK
↑
Receive FIFO Half-full Flag. Active LOW.
When the Receive FIFO is enabled, this signal is asserted (LOW) when the
Receive FIFO is
≥
half full (128 characters). When the Receive FIFO is by-
passed, RXHALF* is deasserted (HIGH).
RXHALF* is forced to the High-Z state only during a
“
full-chip
”
reset (i.e., while
RESET*[1:0] are LOW).
Receive FIFO Empty Flag.
Active LOW when configured for UTOPIA timing, active HIGH when configured
for Cascade timing. When the Receive FIFO is enabled, RXEMPTY* is assert-
ed when no data remains in the Receive FIFO. Any read operation occurring
when RXEMPTY is asserted results in no change in the FIFO status, and the
data from the last valid read remains on the RXDATA bus.
When the Receive FIFO is bypassed but the Decoder is enabled, RXEMPTY*
is used as a valid data indicator. When deasserted it indicates that valid data
(as selected by RXMODE[1:0]) is present at the RXDATA outputs. When as-
serted it indicates that a C5.0 (K28.5) is present on the RXDATA output bus. If
both the Receive FIFO and the Decoder are bypassed, RXEMPTY* is deas-
serted to indicate that all received characters are valid.
Receive FIFO Reset.
When the Receive FIFO is addressed and RXRST* is sampled while asserted
(LOW) for eight or more RXCLK cycles, a Receive FIFO reset is initiated. The
RXRST* input is also asserted to access the Serial Address Register.
Reframe Enable.
Used to control when the framer is allowed to adjust the character boundaries
based on detection of one or more K28.5 characters in the data stream. When
HIGH, the framer is allowed to adjust the character boundaries relative to the
received serial data stream. When LOW, the boundary is fixed.
Receiver BIST Enable.
When active, the receiver is configured to perform a character-for-character
match of the incoming data stream with a 511-character BIST sequence. The
result of character mismatches are indicated on RXRVS. Completion of each
511-character BIST loop is accompanied by an assertion pulse on the
RXFULL* flag.
21
RXEMPTY*
3-state TTL output,
changes following
RXCLK
↑
67
RXRST*
TTL input, sampled
on
RXCLK
↑,
Internal Pull-Up
73
RFEN
TTL input,
asynchronous,
Internal Pull-Up
77
RXBISTEN*
TTL input,
asynchronous,
Internal Pull-Up
Control Signals
71
AM*
TTL input, sampled
by TXCLK
↑
,
RXCLK
↑
, and
REFCLK
↑
Address Match. Active LOW.
Used as a qualifier for TXEN*, RXEN*, TXRST*, and RXRST*. Also controls
three-state enables for the TXFULL*, TXEMPTY*, RXFULL*, and RXEMPTY*
signals.
Serial-in to Serial-out LOOP Select.
This input controls the LOOP-through function in which the serial data is re-
covered by the Clock/Data Recovery PLL and is then retransmitted using the
Transmit PLL as the bit-rate reference. It selects between the output of the
Transmit FIFO and the output of the Elasticity Buffer as the input to the Transmit
Encoder. When LOW, the Transmit FIFO is the source of data for transmission.
When HIGH, the Elasticity Buffer is the source of data for transmission.
Reference Clock.
This clock input is used as the timing reference for the transmit and receive
PLLs. When the Transmit FIFO is bypassed, REFCLK is also used as the clock
for the external transmit data interface.
See
Table 4
for the relationships between REFCLK, SPDSEL, RANGESEL,
and BYTE8/10*.
6
LOOPTX
TTL input,
asynchronous,
Internal Pull-Down
12
REFCLK
TTL input clock
Pin Descriptions
(continued)
CY7C924DX HOTLink Transceiver
Pin #
Name
I/O Characteristics
Signal Description
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PDF描述 |
|---|---|
| CY7C954DX | ATM HOTLink Transceiver(ATM 熱接插收發(fā)器) |
| CY7C964A | Bus Interface Logic Circuit |
| CY7C964A-UM | Bus Interface Logic Circuit |
| CY7C964A-UMB | Bus Interface Logic Circuit |
| CY7C964A-ASC | Bus Interface Logic Circuit |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C9335-270AC | 制造商:Cypress Semiconductor 功能描述:Descrambler/Framer Controller 100-Pin TQFP |
| CY7C9335A-270AXC | 功能描述:網(wǎng)絡控制器與處理器 IC SMPTE Decoder COM RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CY7C9335A-270AXCT | 功能描述:網(wǎng)絡控制器與處理器 IC SMPTE Decoder COM RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CY7C9528-BLC | 制造商:Cypress Semiconductor 功能描述:OC-12/3 (STM-4/1) FRAMER, 504 BGA - Bulk |
| CY7C9528-BLI | 制造商:Cypress Semiconductor 功能描述:OC-12/3 (STM-4/1) FRAMER, 504 BGA - Bulk |
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