參數(shù)資料
型號： CY7C924DX
廠商： Cypress Semiconductor Corp.
英文描述： 200-MBaud HOTLink Transceiver(200H波特?zé)峤硬迨瞻l(fā)器)
中文描述： 200 MBd的的HOTLink收發(fā)器（200小時波特?zé)峤硬迨瞻l(fā)器）
文件頁數(shù)： 25/58頁
文件大?。?/td> 636K
代理商： CY7C924DX
CY7C924DX
PRELIMINARY
25
CY7C924DX DC Electrical Characteristics
Over the Operating Range
Parameter
TTL Outputs
V
OHT
V
OLT
I
OST
I
OZL
TTL Inputs
V
IHT
V
ILT
I
IHT
I
ILT
I
IHPD
I
ILPU
Transmitter PECL-Compatible Output Pins: OUTA+, OUTA
–
, OUTB+, OUTB
–
[7]
V
OHE
Output HIGH Voltage
(V
DD
referenced)
V
OLE
Output LOW Voltage
(V
DD
referenced)
V
ODIF
Output Differential Voltage
|(OUT+)
–
(OUT
–
)|
Receiver Single-ended PECL-Compatible Input Pin: CARDET
V
IHE
Input HIGH Voltage
(V
DD
referenced)
V
ILE
Input LOW Voltage
(V
DD
referenced)
I
IHE
Input HIGH Current
I
ILE
Input LOW Current
Differential Line Receiver Input Pins: INA+, INA
–
, INB+, INB
–
V
DIFF
Input Differential Voltage
|(IN+)
–
(IN
–
)|
V
IHH
Highest Input HIGH Voltage
V
ILL
Lowest Input LOW Voltage
I
IHH
Input HIGH Current
I
ILL[8]
Input LOW Current
Miscellaneous
I
DD [9]
Power Supply Current
Description
Test Conditions
Min.
Max.
Unit
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
High-Z Output Leakage Current
I
OH
=
–
2 mA, V
DD
= Min
I
OL
= 8 mA, V
DD
= Min
V
OUT
= 0V
[6]
2.4
V
V
0.4
–
80
20
–
30
–
20
mA
μ
A
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Input HIGH Current
2.0
–
0.5
V
CC
0.8
+40
–
40
+300
V
V
μ
A
μ
A
μ
A
μ
A
V
IN
= V
CC
V
IN
= 0.0V
V
IN
= V
CC
, Pins with internal pull-down
V
IN
= 0.0V, Pins with internal pull-up
Input LOW Current
–
300
Load = 50
to V
CC
–
1.33V
R
CURSET
= 10k
Load = 50
to V
CC
–
1.33V
R
CURSET
= 10k
Load = 50
to V
CC
–
1.33V
R
CURSET
= 10k
V
DD
–
1.03
V
DD
–
0.83
V
V
DD
–
2
V
DD
–
1.62
V
600
1100
mV
V
DD
–
1.165
V
DD
V
2.5
V
DD
–
1.475
V
V
IN
= V
IHE
(min.)
V
IN
= V
ILE
(max.)
+40
μ
A
μ
A
–
40
200
2500
mV
V
DD
V
V
μ
A
μ
A
2.5
V
IN
= V
IHH
Max.
V
IN
= V
ILL
Min.
750
–
200
Typ.
170
Max.
250
Freq.
= Max.
mA
Capacitance
[10]
Parameter
C
INTTL
C
INPECL
Notes:
6.
Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
7.
The output current and (resulting voltage swing) is set using a single resistor between CURSETx and V
. This CURSET resistor value is calculated as
R
= (100 *Z
)/V
, where Z
is the differential load between the true and compliment outputs of the differential driver.
8.
To guarantee positive currents for all PECL voltages, an external pull-down resistor must be present.
9.
Maximum I
is measured with V
DD
= MAX, RFEN = LOW, and outputs unloaded. Typical I
DD
is measured with V
DD
= 5.0V, T
A
= 25
°
C, RFEN = LOW, and
outputs unloaded.
10. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
Description
Test Conditions
Max.
7
4
Unit
pF
pF
TTL Input Capacitance
PECL input Capacitance
T
A
= 25
°
C, f
0
= 1 MHz, V
DD
= 5.0V
T
A
= 25
°
C, f
0
= 1 MHz, V
DD
= 5.0V
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