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參數(shù)資料
| 型號： | CY7C924DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 200-MBaud HOTLink Transceiver(200H波特?zé)峤硬迨瞻l(fā)器) |
| 中文描述： | 200 MBd的的HOTLink收發(fā)器（200小時波特?zé)峤硬迨瞻l(fā)器） |
| 文件頁數(shù)： | 16/58頁 |
| 文件大小： | 636K |
| 代理商： | CY7C924DX |
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CY7C924DX
PRELIMINARY
16
a C5.0 (K28.5) fill character, which resets the sequencer
boundaries to the first character position.
Encoder Block
The Encoder logic block performs two primary functions: en-
coding the data for serial transmission and generating BIST
(Built-In Self Test) patterns to allow at-speed link and device
testing.
BIST LFSR
The Encoder logic block operates on data stored in a register.
This register accepts information directly from the Transmit
FIFO, the Transmit Input Register, the 10/8 Byte-Packer, or
from the Transmit Control State Machine when it inserts spe-
cial characters into the data stream.
This same register is converted into a Linear Feedback Shift
Register (LFSR) when the Built-In Self-Test (BIST) pattern
generator is enabled (TXBISTEN* is LOW). When enabled,
this LFSR generates a 511-character sequence that includes
all Data and Special Character codes, including the explicit
violation symbols. This provides a predictable but pseudo-
random sequence that can be matched to an identical LFSR
in the Receiver.
The specific patterns generated are described in detail in the
Cypress application note
“
HOTLink Built-In Self-Test.
”
The se-
quence generated by the CY7C924DX is identical to that in the
CY7B923 and CY7C929, allowing interoperable systems to be
built when used at compatible serial signaling rates.
Encoder
The data passed through the Transmit FIFO and formatter, or
as received directly from the Transmit Input Register, is seldom
in a form suitable for transmission across a serial link. The
characters must usually be processed or transformed to guar-
antee:
a minimum transition density (to allow the serial receiver
PLL to extract a clock from the data stream)
a DC-balance in the signaling (to prevent baseline wander)
run-length limits in the serial data (to limit the bandwidth of
the link)
some way to allow the remote receiver to determine the
correct character boundaries (framing).
The CY7C924DX contains an integrated 8B/10B encoder that
accepts 8-bit data characters and converts these into 10-bit
transmission characters that have been optimized for transport
on serial communications links. The 8B/10B encoder can be
bypassed for those system that operate with external 8B/10B
encoders, or use alternate forms of encoding or scrambling to
ensure good transmission characteristics. The operation of the
8B/10B encoding algorithm is described in detail later in this
data sheet, and the complete encoding tables are listed in
Ta-
bles 10
and
11
.
When the Encoder is enabled, the transmit data characters (as
passed through the Transmit FIFO and formatter) are converted to
either a 10-bit Data symbol or a 10-bit Special Character, depending
upon the state of the TXSC/D* input. If TXSC/D* is HIGH, the data
inputs represent a Special Character code and are encoded using
the Special Character encoding rules in
Table 11
. If TXSC/D* is
LOW, the data inputs are encoded using the Data Character encod-
ing in
Table 10
.
When operated without parity checking, the MSB of each char-
acter is used to override the contents of the remaining bits in
the character. If this bit (TXSVS) is HIGH, the respective char-
acter is replaced with an SVS (C0.7) character. This can be
used to check error handling system-logic in the receiver control-
ler or for proprietary applications.
The 8B/10B encoder is standards compliant with ANSI/NCITS
ASC X3.230-1994 (Fibre Channel), IEEE 802.3z (Gigabit
Ethernet), the IBM ESCON and FICON channels, and ATM
Forum standards for data transport.
The 8B/10B coding function of the Encoder can be bypassed
for systems that include an external coder or scrambler func-
tion as part of the controller or host system. This is performed
by setting ENCBYP* LOW. With the encoder bypassed, each
10-bit character (as captured in the Transmit Input Register) is
passed directly to the Transmit Shifter (or Transmit FIFO) with-
out modification.
Transmit Shifter
The Transmit Shifter accepts 10-bit parallel data from the En-
coder block once each character time, and shifts it out the
serial interface output buffers using a PLL-multiplied bit-clock.
This bit-clock runs at 2.5, 5, or 10 times the REFCLK rate (3,
6, or 12 times when BYTE8/10* is LOW) as selected by
RANGESEL and SPDSEL (see
Table 4
). Timing for the parallel
transfer is controlled by the counter and dividers in the Clock
Multiplier PLL and is not affected by signal levels or timing at
the input pins.
Bits in each character are shifted out LSB first, as required by
ANSI and IEEE standards for 8B/10B coded serial data
streams.
Routing Matrix
The Routing Matrix is a set of precision multiplexors that allow
various combinations of Transmit Shifter, buffered INA
±
or
INB
±
serial line receiver inputs, or a reclocked serial line re-
ceiver input to be transmitted from the OUTB
±
serial data out-
puts. The signal routing for the transmit serial outputs is con-
trolled primarily by the DLB[1:0] inputs as listed in
Table 3
.
Figure 4. Byte-Packer 10-to-8 Character Mapping
AAAAAAAA
76543210
First
Character
Sent
BBBBBBAA
54321098
DDDDDDDD
98765432
DDCCCCCC
10987654
CCCCBBBB
32109876
Last
Character
Sent
Source 10-bit Character Stream
DDDDDDDDDD
9876543210
CCCCCCCCCC
9876543210
BBBBBBBBBB
9876543210
AAAAAAAAAA
9876543210
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