- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378513 > CY7C924DX (Cypress Semiconductor Corp.) 200-MBaud HOTLink Transceiver(200H波特熱接插收發(fā)器) PDF資料下載
參數(shù)資料
| 型號： | CY7C924DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 200-MBaud HOTLink Transceiver(200H波特熱接插收發(fā)器) |
| 中文描述： | 200 MBd的的HOTLink收發(fā)器（200小時波特熱接插收發(fā)器） |
| 文件頁數(shù)： | 19/58頁 |
| 文件大?。?/td> | 636K |
| 代理商： | CY7C924DX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁
CY7C924DX
PRELIMINARY
19
when sending non-8B/10B coded data streams, or data
streams that cannot tolerate the data forwarding policies of the
Elasticity Buffer.
This reclocked output stream may also be beneficial in sys-
tems requiring very low latency. The internal data delays for a
reclocked serial stream are a small number of bits, while data
sent through the Elasticity Buffer incurs a delay of a small num-
ber of characters.
Signal Detect
The selected Line Receiver (that routed to the clock and data
recovery PLL) is simultaneously monitored for:
analog amplitude (>400 mV pk-pk)
transition density
received data stream outside normal frequency range
(
±
400 ppm)
and carrier detected.
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFI* (Link Fault Indicator) output, which changes synchro-
nous to RXCLK. While link status is monitored internally at all
times, it is necessary to have transitions on RXCLK to allow
this signal to change externally.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of data bits from
the received serial stream is performed within the Clock/Data
Recovery (CDR) block. The clock extraction function is per-
formed by a high-performance embedded phase-locked loop
(PLL) that tracks the frequency of the incoming bit stream and
aligns the phase of its internal bit-rate clock to the transitions
in the serial data stream.
The CDR makes use of the clock present at the REFCLK input.
It is used to ensure that the VCO (within the CDR) is operating
at the correct frequency (rather than some harmonic of the bit
rate), to improve PLL acquisition time, and to limit unlocked
frequency excursions of the CDR VCO when no data is
present at the serial inputs.
Regardless of the type of signal present, the CDR will attempt
to recover a data stream from it. If the frequency of the recov-
ered data stream is outside the limits for the range controls,
the CDR PLL will track REFCLK instead of the data stream.
When the frequency of the selected data stream returns to a
valid frequency, the CDR PLL is allowed to track the received
data stream. The frequency of REFCLK is required to be within
±
400 ppm of the frequency of the clock that drives the REFCLK
signal at the remote transmitter to ensure a lock to the incom-
ing data stream.
For systems using multiple or redundant connections, the LFI*
output can be used to select an alternate data stream. When
an LFI* indication is detected, external logic can toggle selec-
tion of the INA
±
and INB
±
inputs through the A/B* input. When
a port switch takes place, it is necessary for the PLL to re-
acquire the new serial stream and frame to the incoming char-
acters.
Clock Divider
This block contains the clock division logic, used to transfer the
data from the Deserializer/Framer to the Decoder once every
character (once every ten or twelve bits) clock. This counter is
free running and generates outputs at the bit-rate divided by
10 (12 when the BYTE8/10* and ENCBYP* are LOW). When
the Receive FIFO is bypassed, one of these generated clocks
is driven out the RXCLK pin.
Deserializer/Framer
The CDR circuit extracts bits from the serial data stream and
clocks these bits into the Shifter/Framer at the bit-clock rate.
When enabled, the Framer examines the data stream looking
for C5.0 (K28.5) characters at all possible bit positions. The
location of this character in the data stream is used to deter-
mine the character boundaries of all following characters.
The framer operates in one of three different modes, as select-
ed by the RFEN input. When RFEN is first asserted (HIGH),
the framer is allowed to reset the internal character boundaries
on any detected C5.0 character.
Once RFEN has been HIGH for greater than approximately
2000 character clock cycles, the multi-byte framer is enabled.
This requires two C5.0 characters within a span of five char-
acters, with both C5.0 characters located on identical 10-bit
character boundary locations, before the framer is allowed to
reset the internal character boundary.
If RFEN is LOW, the framer is disabled and no changes are
made to character boundaries.
The framer in the CY7C924DX operates by shifting the internal
character position to align with the character clock. This en-
sures that the recovered clock does not contain any significant
phase changes/hops during normal operation or framing, and
allows the recovered clock to be replicated and distributed to
other circuits using PLL-based logic elements.
Decoder Block
The decoder logic block performs two primary functions: de-
coding the received transmission characters back into Data
and Special Character codes, and comparing generated BIST
patterns with received characters to permit at-speed link and
device testing.
10B/8B Decoder
The framed parallel output of the Deserializer is passed to the
10B/8B Decoder where, if the Decoder is enabled, it is trans-
formed from a 10-bit transmission character back to the origi-
nal Data and Special Character codes. This block uses the
standard decoder patterns in
Tables 10
and
11
of this data
sheet. Data patterns are indicated by a LOW on RXSC/D*, and
Special Character codes are indicated by a HIGH. Invalid patterns
or disparity errors are signaled as errors by a HIGH on RXRVS, and
by specific Special Character codes.
If the Decoder is bypassed and BYTE8/10* is HIGH, the ten
(10) data bits of each transmission character are passed un-
changed from the framer to the Pipeline Register.
When the Decoder is bypassed and BYTE8/10* is LOW, the
twelve (12) data bits of each transmission character are
passed unchanged from the framer to the Pipeline Register.
BIST LFSR
The output register of the Decoder block is normally used to
accumulate received characters for delivery to the Receive
Formatter
block.
When
configured
(RXBISTEN* is LOW), this register becomes a signature pat-
tern generator and checker by logically converting to a Linear
Feedback Shift Register (LFSR). When enabled, this LFSR
for BIST mode
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C954DX | ATM HOTLink Transceiver(ATM 熱接插收發(fā)器) |
| CY7C964A | Bus Interface Logic Circuit |
| CY7C964A-UM | Bus Interface Logic Circuit |
| CY7C964A-UMB | Bus Interface Logic Circuit |
| CY7C964A-ASC | Bus Interface Logic Circuit |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C9335-270AC | 制造商:Cypress Semiconductor 功能描述:Descrambler/Framer Controller 100-Pin TQFP |
| CY7C9335A-270AXC | 功能描述:網(wǎng)絡控制器與處理器 IC SMPTE Decoder COM RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CY7C9335A-270AXCT | 功能描述:網(wǎng)絡控制器與處理器 IC SMPTE Decoder COM RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CY7C9528-BLC | 制造商:Cypress Semiconductor 功能描述:OC-12/3 (STM-4/1) FRAMER, 504 BGA - Bulk |
| CY7C9528-BLI | 制造商:Cypress Semiconductor 功能描述:OC-12/3 (STM-4/1) FRAMER, 504 BGA - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。