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參數(shù)資料
| 型號(hào)： | CY7C924DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 200-MBaud HOTLink Transceiver(200H波特?zé)峤硬迨瞻l(fā)器) |
| 中文描述： | 200 MBd的的HOTLink收發(fā)器（200小時(shí)波特?zé)峤硬迨瞻l(fā)器） |
| 文件頁數(shù)： | 35/58頁 |
| 文件大?。?/td> | 636K |
| 代理商： | CY7C924DX |
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CY7C924DX
PRELIMINARY
35
CY7C924DX HOTLink Transceiver
Operation
The interconnection of two or more CY7C924DX Transceivers
form a general-purpose communications subsystem capable
of transporting user data at up to 20 MBytes per second over
several types of serial interface media. The CY7C924DX is
highly configurable with multiple modes of operation.
In the transmit section of the CY7C924DX, data moves from
the input register, through the Transmit FIFO, to the 8B/10B
Encoder. The encoded data is then shifted serially out the
OUTx
±
differential PECL compatible drivers. The bit-rate clock
is generated internally from a 2.5x, 5x, or 10x PLL clock mul-
tiplier. A more complete description is found in the section
CY7C924DX HOTLink Transmit-Path Operating Mode De-
scription
.
In the receive section of the CY7C924DX, serial data is sam-
pled by the receiver on one of the INx
±
differential line receiver
inputs. The receiver clock and data recovery PLL locks onto
the selected serial bit stream and generates an internal bit-rate
sample clock. The bit stream is deserialized, decoded, and
presented to the Receive FIFO, along with a character clock.
The data in the FIFO can then be read either slower or faster
than the incoming character rate. A more complete description
is found in the section
CY7C924DX HOTLink Receive-Path
Operating Mode Description
.
The Transmitter and Receiver parallel interface timing and
functionality can be configured to Cascade directly to external
FIFOs for depth expansion, to emulate a UTOPIA interface,
couple directly to registers, or couple directly to state ma-
chines. These interfaces can accept or output either:
8-bit characters
10-bit characters (for byte-packed encoded transport)
10-bit pre-encoded characters (pre-scrambled or
pre-encoded)
12-bit pre-encoded characters (pre-scrambled or
pre-encoded)
The bit numbering and content of the parallel transmit interface
is shown in
Table 1
. When operated with the 8B/10B Encoder
bypassed, the TXSC/D* and RXSC/D* bits are ignored.
The HOTLink Transceiver serial interface provides a seamless
interface to various types of media. A minimal number of ex-
ternal passive components are required to properly terminate
transmission lines and provide LVPECL loads. For power sup-
ply decoupling, a single capacitor (in the range of 0.02
μ
F to
0.1
μ
F) is required per power/ground pair. Additional informa-
tion on interfacing these components to various media can be
found in the
HOTLink Design Considerations
application note.
CY7C924DX HOTLink Transmit-Path
Operating Mode Descriptions
The HOTLink Transmitter can be configured into several oper-
ating modes, each providing different capabilities and fitting
different transmission needs. These modes are selected using
the FIFOBYP*, ENCBYP* and BYTE8/10* inputs on the
CY7C924DX Transceiver. These modes can be reduced to five
primary classes:
Synchronous Encoded
Synchronous Pre-encoded
Asynchronous Encoded
Asynchronous Byte-Packed
Asynchronous Pre-encoded
Synchronous Encoded
In this mode, the Transmit FIFO is bypassed, while the 8B/10B
encoder is enabled. One character is accepted at the Transmit
Input Register at the rising edge of REFCLK, and passed to
the Encoder where it is encoded for serial transmission. The
Serializer operates synchronous to REFCLK, which is multi-
plied by 10 or 5 to generate the serial data bit-clock. In this
mode the TXSOC, TXRST*, TXINT, TXHALT*, and TXSTOP*
inputs (when they are not used for data bits) are not interpreted
and may be tied either HIGH or LOW. To place the
CY7C924DX into synchronous modes, FIFOBYP* must be
LOW.
This mode is usually used for products that must meet specific
predefined protocol requirements, and cannot tolerate the un-
controlled insertion of C5.0 fill characters. The host system is
required to provide new data at every rising edge of REFCLK
(along with TXEN*) to maintain the data stream. If TXEN* is
not asserted, the Encoder is loaded with C5.0 (K28.5) sync
characters. Because the Encoder is enabled, the transmitted
C5.0 characters follow all 8B/10B encoding rules.
Input Register Mapping
In Encoded modes, the bits of the TXDATA input bus are
mapped into characters (as shown in
Table 1
), including a
TXSVS bit, eight bits of data, and a TXSC/D* bit to select either
Special Character codes or Data characters. When the inter-
nal FIFO is enabled, TXINT and TXSOC bits are associated
with the TXDATA bus. When the internal FIFO is disabled
TXPAREN and TXOPIN are associated with the TXDATA bus.
When parity generation is enabled (TXPAREN is HIGH) the
TXOPIN bit is interpreted as the ODD parity for the remaining
bits of the character. When parity generation is disabled
(TXPAREN is LOW) the TXOPIN bit is ignored
If the TXSVS bit is HIGH, an SVS (C0.7) character is passed
to the encoder, regardless of the contents of the other TXDATA
inputs. If the TXSVS bit is LOW, the associated TXDATA char-
acter is encoded per the remaining bits in that character.
The TXSC/D* bit controls the encoding of the TXDATA[7:0] or
TXDATA[9:0] bits of each character. It is used to identify if the
input character represents a Data Character or a Special
Character code. If TXSC/D* is LOW, the character is encoded
using the Data Character codes listed in
Table 10
. If TXSC/D*
is HIGH, the character is encoded using the Special Character
codes listed in
Table 11
.
Parity
Synchronous Encoded operation allows parity checking of all
characters written to the Transmit Input Register. If a parity
error is detected the TXPERR output goes HIGH for one
REFCLK period.
The specific character or characters having parity errors are
replaced at the Encoder with the SVS (C0.7) character, which
may then be detected at the remote receiver.
Synchronous Pre-encoded
In synchronous pre-encoded mode, both the Transmit FIFO
and the 8B/10B encoder are bypassed, and data passes di-
rectly from the Transmit Input Register to the Serializer. The
Serializer operates synchronous to REFCLK, which is multi-
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