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參數(shù)資料
| 型號： | CY7C924DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 200-MBaud HOTLink Transceiver(200H波特?zé)峤硬迨瞻l(fā)器) |
| 中文描述： | 200 MBd的的HOTLink收發(fā)器（200小時(shí)波特?zé)峤硬迨瞻l(fā)器） |
| 文件頁數(shù)： | 36/58頁 |
| 文件大?。?/td> | 636K |
| 代理商： | CY7C924DX |
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CY7C924DX
PRELIMINARY
36
plied by 10 or 5 when BYTE8/10* is HIGH (as selected by the
SPDSEL and RANGESEL inputs) to generate the serial data
bit-clock. In this mode the TXINT, TXHALT*, TXSVS and
TXSOC inputs are used as part of the data input bus. To place
the CY7C924DX into synchronous modes, FIFOBYP* must be
LOW.
This mode is usually used for products containing external en-
coders or scramblers, that must meet specific protocol require-
ments. The host system is required to provide new data at
every rising edge of the REFCLK (along with TXEN*) to main-
tain the data stream. If TXEN* is not asserted, the Serializer is
loaded with C5.0 (K28.5) sync characters. However, because
the bypassed encoder is not able to track the running disparity
of the previously transmitted character, the transmitted C5.0
characters may be received with a running disparity code-rule
violation.
In this mode the LSB of each input character (TXDATA[0]) is
shifted out first, followed sequentially by TXDATA[1] through
TXDATA[9].
Asynchronous Encoded
Asynchronous Encoded mode is the most powerful operating
mode of the CY7C924DX. Both the Transmit FIFO and the
Encoder are enabled. This allows transmission of normal data
streams, while offering the added benefits of embedded cell or
packet markers, an expanded command set, serial address-
ing, and in-band bypass-signaling (for flow control or other pur-
poses). The Serializer operates synchronous to REFCLK,
which is multiplied by 2.5, 5, or 10 to generate the serial data
bit-clock (as selected by SPDSEL and RANGESEL). In this
mode the TXSOC, TXRST*, TXINT, TXHALT*, and TXSTOP*
inputs are interpreted.
This mode supports the same Input Register mapping as Syn-
chronous Encoded mode, with the addition of the TXSOC bit.
Because both the Transmit FIFO and Encoder are enabled, the
input FIFO may be loaded at any rate supported by the FIFO
(up to 50 MHz), without generating any decoder errors at the
receive end of the link. All characters added to the data stream
to support these additional capabilities may be automatically
extracted by the Receive Control State Machine in the
CY7C924DX Receiver.
Embedded Cell Marker
An embedded cell marker is used to mark the start of cells or
frames of information passed from one end of the link to the
other. This marker is set by asserting TXSOC HIGH, with
TXSC/D* and TXSVS both LOW, along with the remaining
data on the TXDATA bus. When the character (or characters)
accompanying this marker is read from the output end of the
Transmit FIFO, a C8.0 (K23.7) character is inserted into the
data stream prior to the following data characters being read
from the Transmit FIFO.
Expanded Commands
The standard 8B/10B Character set contains all 256 possible
data characters, but only twelve special or
command
charac-
ters. To allow use of a larger selection of command codes, a
Special Character code was selected to expand the command
set.
An expanded command marker is used to mark the associated
data as any one of 256 (2
8
) possible commands codes. This
marker is generated by asserting both TXSOC and TXSC/D*
HIGH, with TXSVS being LOW, along with the associated data
on the TXDATA bus. When the character accompanying this
marker is read from the output end of the Transmit FIFO, a
C9.0 (K27.7) character is inserted into the data stream prior to
the data characters read from the Transmit FIFO.
Serial Addressing
The CY7C924DX receiver has the ability to accept or reject
data based on an internal address-controlled switch. This
switch is turned on when a serial address (matching the re-
ceiver address settings) is received.
A serial address is transmitted by asserting TXSOC, TXSC/D*,
and TXSVS all HIGH. When the character accompanying this
marker is read from the output end of the Transmit FIFO, a
C10.0 (K29.7) character is inserted into the data stream prior
to the data characters read from the Transmit FIFO. The serial
address is either 8 or 10.bits depending on the level on
BYTE8/10*.
In-Band Bypass-Signaling
In-band bypass-signaling allows a signal to be sent to the re-
mote receiver without that signal having to pass through the
Transmit (or Receive) FIFO.
When TXINT transitions from 0
→
1, a C0.0 (K28.0) special
character is sent. When TXINT transitions from 1
→
0, a C3.0
(K28.3) special code is sent. These special codes may be
used to force a similar signal transition on the RXINT output of
an attached CY7C924DX HOTLink Receiver.
This input may be used to transport a low data rate signal (like
a serial RS-232/UART signal) across the interface, without any
significant impact on the actual data being transported across
the link. It may also be used to transparently propagate FIFO
flow control information across the link by directly connecting
the RXHALF* flag of the local receiver to the TXINT of the local
transmitter. The RXINT at the remote end of the link can then
be connected to the TXHALT* input to halt data transfers at the
remote end of the link until the local Receive FIFO has suffi-
cient room to continue.
Asynchronous Byte-Packed
Asynchronous byte-packed mode contains the same features
as asynchronous encoded, but with support for 10-bit source
data. This data is byte-packed through the 8B/10B encoder to
deliver the data across the interface.
When sending extended commands, the larger 10-bit charac-
ter size enlarges the extended command space to 1024 (2
10
)
possible commands codes.
Asynchronous Pre-encoded
In Asynchronous pre-encoded modes, the Transmit FIFO is
enabled. This means that all words clocked into the input reg-
ister are written to the Transmit FIFO before being sent to the
Serializer. The Serializer operates synchronous to REFCLK,
which is multiplied by 10 or 5 (or 6 or 12 when BYTE8/10* is
LOW) to generate the serial data bit-clock. In this mode the
TXINT and TXHALT* inputs are used as part of the 10-bit input
character. TXSVS, TXSOC and TXSTOP* are still available to
stop reading of data from the Transmit FIFO.
These modes are usually used for products containing exter-
nal encoders or scramblers, that must meet specific protocol
requirements. The host system must provide new data at ev-
ery rising edge of TXCLK (along with TXEN*) to maintain the
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