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參數(shù)資料
| 型號： | CY7C924DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 200-MBaud HOTLink Transceiver(200H波特熱接插收發(fā)器) |
| 中文描述： | 200 MBd的的HOTLink收發(fā)器（200小時波特熱接插收發(fā)器） |
| 文件頁數(shù)： | 23/58頁 |
| 文件大?。?/td> | 636K |
| 代理商： | CY7C924DX |
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CY7C924DX
PRELIMINARY
23
RXHALF*, to implement a back-pressure mechanism for the
Receive FIFO, or for other time dependent signalling.
If the Receive FIFO and Decoder are bypassed, all received
characters are passed directly to the Receive Output Register.
If framing is enabled, and K28.5 characters have been detect-
ed meeting the present framing requirements, the output char-
acters will appear on proper character boundaries. If framing
is disabled (RFEN is LOW) or K28.5 characters have not been
detected in the data stream, the received characters may not
be output on their proper 10-bit boundaries. In this mode,
some form of external framing and decoding/descrambling
must be used to recover the original source data.
Serial Address Register
The receiver is capable of selectively accepting or discarding
received data based on an address received in the data
stream. The address matching capability allows for the choice
of matching of either domains (multicast) or exact addresses
(unicast). The 8- or 10-bit Serial Address Register represents
a single character address field as shown in
Figure 6
.
The multicast mode is bit-specific and allows allocation of up
to 8 or 10 separate domains. In the unicast address mode the
match is character specific and identifies up to 256 or 1024
destination addresses. A device can either belong to one or
more domains, or it can have a single unique address.
When a serial address is received and a match is detected, the
address, and all data following that address, is passed to the
Receive FIFO (except in discard policy 3 where the address is
discarded). This continues until a serial address is received
that does not match the contents of the Address Register,
whereupon writes to the Receive FIFO are inhibited.
The Serial Address Register has a power-up default state
where the multicast field set to an all ones condition (FFh or
3FFh). When set to this value the receiver accepts all data,
regardless of the of the presence or content of any received
serial address. This
“
promiscuous
”
address can also be forced
by the momentary assertion of the RESET*[1:0] pair.
The Serial Address Register is only used when the receiver is
operated with the Receive FIFO enabled (FIFOBYP* is HIGH)
and in operating modes where the discard policy is not 0 (see
Table 6
for a list of discard policies).
Serial Address Register Access
The Serial Address Register is accessed through the RXDATA
bus. Both reads and writes to the register require the device to
be addressed (AM* is LOW) and for RXRST* to be asserted
(LOW).
When accessed for write or read operations, the RXRVS signal
is used as a read/write selector, and RXSC/D* is used to select
the operating mode (multicast or unicast) of the Serial Address
Register.
Table 7. Receive Output Bus Signal Map
Receive Decoder Mode
[1]
Decoded 10-bit
Character Stream
(8-bit characters)
HIGH
Undecoded 10-bit
Character Stream
LOW
Decoded 10-bit
Byte-Packed
Character Stream
(10-bit characters)
HIGH
Undecoded 12-bit
Character Stream
LOW
ENCBYP*
BYTE8/10*
RXDATA Bus I/O Bit
HIGH
HIGH
LOW
LOW
RXSC/D*
RXSC/D*
RXSC/D*
RXDATA[0]
RXD[0]
RXD[0]
[5]
RXD[0]
RXD[0]
[5]
RXDATA[1]
RXD[1]
RXD[1]
RXD[1]
RXD[1]
RXDATA[2]
RXD[2]
RXD[2]
RXD[2]
RXD[2]
RXDATA[3]
RXD[3]
RXD[3]
RXD[3]
RXD[3]
RXDATA[4]
RXD[4]
RXD[4]
RXD[4]
RXD[4]
RXDATA[5]
RXD[5]
RXD[5]
RXD[5]
RXD[5]
RXDATA[6]
RXD[6]
RXD[6]
RXD[6]
RXD[6]
RXDATA[7]
RXD[7]
RXD[7]
RXD[7]
RXD[7]
RXINT/RXOP/RXDATA[8]
(FIFOBYP*=HIGH)
RXINT
RXD[8]
RXD[8]
RXD[8]
RXINT/RXOP/RXDATA[8]
(FIFOBYP*=LOW)
RXOP
RXD[8]
RXD[8]
RXD[8]
RXDATA[9]
(LOW)
RXD[9]
RXD[9]
RXD[9]
RXRVS/RXDATA[10]
RXRVS
RXRVS
RXD[10]
RXSOC/RXDATA[11]
RXSOC
RXSOC
RXD[11]
Note:
5.
First bit shifted in. Others follow in numerical order interpreted from an NRZ pattern.
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