參數(shù)資料
型號(hào)： CY3687
廠商： Cypress Semiconductor Corp.
英文描述： MoBL-USB⑩ FX2LP18 USB Microcontroller
中文描述： 的MoBL - USB FX2LP18的USB微控制器⑩
文件頁(yè)數(shù)： 36/39頁(yè)
文件大小： 453K
代理商： CY3687
CY7C68053
Document # 001-06120 Rev *H
Page 36 of 39
9.13.4 Sequence Diagram of a Single and Burst Asynchronous Write
Figure 25
illustrates the timing relationship of the SLAVE FIFO
write in an asynchronous mode. The diagram shows a single
write followed by a burst write of 3 bytes and committing the
4-byte-short packet using PKTEND.
■
At t = 0 the FIFO address is applied, ensuring that it meets the
setup time of t
SFA
. If SLCS is used, it must also be asserted
(SLCS may be tied low in some applications).
■
At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of t
WRpwl
and minimum inactive pulse width of
t
WRpwh
. If the SLCS is used, it must be asserted before SLWR
is asserted.
■
At t = 2, data must be present on the bus t
SFD
before the
deasserting edge of SLWR.
■
At t = 3, deasserting SLWR causes the data to be written from
the data bus to the FIFO and then the FIFO pointer is incre-
mented. The FIFO flag is also updated after t
XFLG
from the
deasserting edge of SLWR.
The same sequence of events is shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note
In the
burst write mode, once SLWR is deasserted, the data is written
to the FIFO and then the FIFO pointer is incremented to the next
byte in the FIFO. The FIFO pointer is post incremented.
In
Figure 25
once the four bytes are written to the FIFO and
SLWR is deasserted, the short 4-byte packet can be committed
to the host using the PKTEND. The external device must be
designed to not assert SLWR and the PKTEND signal at the
same time. It must be designed to assert the PKTEND after
SLWR is deasserted and meet the minimum deasserted pulse
width. The FIFOADDR lines are to be held constant during the
PKTEND assertion.
PKTEND
SLWR
FLAGS
DATA
Figure 25. Slave FIFO Asynchronous Write Sequence and Timing Diagram
[17]
t
WRpwh
t
WRpwl
t
XFLG
N
t
SFD
N+1
t
XFLG
t
SFA
t
FAH
FIFOADR
SLCS
t
WRpwh
t
WRpwl
t
WRpwh
t
WRpwl
t
WRpwh
t
WRpwl
t
FAH
t
SFA
t
FDH
t
SFD
N+2
t
FDH
t
SFD
N+3
t
FDH
t
SFD
t
FDH
t
PEpwh
t
PEpwl
t=0
t=2
t =1
t=3
T=0
T=2
T=1
T=3
T=6
T=9
T=5
T=8
T=4
T=7
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CY3688 功能描述:界面開(kāi)發(fā)工具 CY3688 RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
CY3690 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 USB 2.0 DVEL KIT RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類(lèi)型:I2C, SPI, USB 工作電源電壓:
CY3691 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 USB 2.0 DVEL KIT RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類(lèi)型:I2C, SPI, USB 工作電源電壓:
CY3692 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 Socket adapter "for CY23FP12" RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類(lèi)型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
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